Development of FPGA based phase alignment logic for the high speed protocol in HEP Experiments

Experiments in high energy physics (HEP) operate at the forefront of detector technology, electronics, data acquisition (DAQ), data analysis, and computing. With the advent of high-energy accelerators running at large beam intensities, there is a great demand for radiation-hard high speed protocol for data transmission. Along with the detector data, communication signals like trigger, timing and control (TTC) information plays an important role. The TTC information needs to be transmitted over long distances using asynchronous communication links, which act as a bridge between the front-end radiation hard electronics and the DAQ. Maintaining the timing relationships and synchronization among payloads is an essential pre-requisite for the integrity of the acquired data. However, the phase relationship among the transmitted TTC signals gets disrupted due to the various sources of inter-signal interferences and channel link uncertainties. To address this challenge we have developed a phase alignment logic that can be applied over any asynchronous data-transmission protocol. We have implemented the proposed logic on the widely used radiation tolerant data-transmission protocol, called Gigabit Transceiver (GBT). The DAQ architecture needs to be resilient enough to avoid the loss of data or the errors in physics payload. The principal idea for implementation of the logic is to have an effective strategy to realign the synchronization without the need for power-on reset (PoR). The approach reduces the number of dead cycles that otherwise would have been utilized to minimize the timing errors. The chosen hardware for the experimental setup is 28 nm Stratix-V FPGA from Intel Inc. The benchmark of the system performance is illustrated in terms of the measurements of resource utilization, results of signal integrity, route delays, eye diagram and jitter analysis.