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Improving the High-Temperature Gate Bias Instabilities by a Low Thermal Budget Gate-First Process in p-GaN Gate HEMTs

In this study, we report a low ohmic contact resistance process on a 650 V E-mode p-GaN gate HEMT structure. An amorphous silicon (a-Si) assisted layer was inserted in between the ohmic contact and GaN. The fabricated device exhibits a lower contact resistance of about 0.6 Ω-mm after annealing at 55...

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Detalles Bibliográficos
Autores principales:	Langpoklakpam, Catherine, Liu, An-Chen, You, Neng-Jie, Kao, Ming-Hsuan, Huang, Wen-Hsien, Shen, Chang-Hong, Tzou, Jerry, Kuo, Hao-Chung, Shieh, Jia-Min
Formato:	Online Artículo Texto
Lenguaje:	English
Publicado:	MDPI 2023
Materias:	Article
Acceso en línea:	https://www.ncbi.nlm.nih.gov/pmc/articles/PMC10051557/ https://www.ncbi.nlm.nih.gov/pubmed/36984983 http://dx.doi.org/10.3390/mi14030576

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