Effect of Gate Bias Stress on the Electrical Characteristics of Ferroelectric Oxide Thin-Film Transistors with Poly(Vinylidenefluoride-Trifluoroethylene)

We investigated the effect of gate bias stress (GBS) on the electrical characteristics of ferroelectric oxide thin-film transistors (FeOxTFTs) with poly(vinylidenefluoride-trifluoroethylene). Generally, conventional oxide thin-film transistors (OxTFTs) with dielectric gate insulators exhibit a small negative shift under negative gate bias stress (NBS) and a large positive shift under positive gate bias stress (PBS) in transfer characteristic curves. In contrast, the FeOxTFTs show a small positive shift and a large negative shift under NBS and PBS, respectively. It was confirmed that sufficient changes in the electrical characteristics are obtained by 10 min NBS and PBS. The changed electrical characteristics such as threshold voltage shift, memory on- and memory off-current were maintained for more than 168 h after NBS and 24 h after PBS. It is deduced that, since the dipole alignment of the ferroelectric layer is maximized during GBS, these changes in electrical properties are caused by the remnant dipole moments still being retained during the gate sweep. The memory on- and memory off-current are controlled by GBS and the best on/off current ratio at 10(7) was obtained after NBS. By repeatedly alternating NBS and PBS, the electrical characteristics were reversibly changed. Our results provide the scientific and technological basis for the development of stability and performance optimization of FeOxTFTs.