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A Low-Power Analog Integrated Implementation of the Support Vector Machine Algorithm with On-Chip Learning Tested on a Bearing Fault Application

A novel analog integrated implementation of a hardware-friendly support vector machine algorithm that can be a part of a classification system is presented in this work. The utilized architecture is capable of on-chip learning, making the overall circuit completely autonomous at the cost of power an...

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Autores principales: Alimisis, Vassilis, Gennis, Georgios, Gourdouparis, Marios, Dimas, Christos, Sotiriadis, Paul P.
Formato: Online Artículo Texto
Lenguaje:English
Publicado: MDPI 2023
Materias:
Acceso en línea:https://www.ncbi.nlm.nih.gov/pmc/articles/PMC10145287/
https://www.ncbi.nlm.nih.gov/pubmed/37112319
http://dx.doi.org/10.3390/s23083978
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author Alimisis, Vassilis
Gennis, Georgios
Gourdouparis, Marios
Dimas, Christos
Sotiriadis, Paul P.
author_facet Alimisis, Vassilis
Gennis, Georgios
Gourdouparis, Marios
Dimas, Christos
Sotiriadis, Paul P.
author_sort Alimisis, Vassilis
collection PubMed
description A novel analog integrated implementation of a hardware-friendly support vector machine algorithm that can be a part of a classification system is presented in this work. The utilized architecture is capable of on-chip learning, making the overall circuit completely autonomous at the cost of power and area efficiency. Nonetheless, using subthreshold region techniques and a low power supply voltage (at only 0.6 V), the overall power consumption is 72 μW. The classifier consists of two main components, the learning and the classification blocks, both of which are based on the mathematical equations of the hardware-friendly algorithm. Based on a real-world dataset, the proposed classifier achieves only 1.4% less average accuracy than a software-based implementation of the same model. Both design procedure and all post-layout simulations are conducted in the Cadence IC Suite, in a TSMC 90 nm CMOS process.
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spelling pubmed-101452872023-04-29 A Low-Power Analog Integrated Implementation of the Support Vector Machine Algorithm with On-Chip Learning Tested on a Bearing Fault Application Alimisis, Vassilis Gennis, Georgios Gourdouparis, Marios Dimas, Christos Sotiriadis, Paul P. Sensors (Basel) Article A novel analog integrated implementation of a hardware-friendly support vector machine algorithm that can be a part of a classification system is presented in this work. The utilized architecture is capable of on-chip learning, making the overall circuit completely autonomous at the cost of power and area efficiency. Nonetheless, using subthreshold region techniques and a low power supply voltage (at only 0.6 V), the overall power consumption is 72 μW. The classifier consists of two main components, the learning and the classification blocks, both of which are based on the mathematical equations of the hardware-friendly algorithm. Based on a real-world dataset, the proposed classifier achieves only 1.4% less average accuracy than a software-based implementation of the same model. Both design procedure and all post-layout simulations are conducted in the Cadence IC Suite, in a TSMC 90 nm CMOS process. MDPI 2023-04-14 /pmc/articles/PMC10145287/ /pubmed/37112319 http://dx.doi.org/10.3390/s23083978 Text en © 2023 by the authors. https://creativecommons.org/licenses/by/4.0/Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https://creativecommons.org/licenses/by/4.0/).
spellingShingle Article
Alimisis, Vassilis
Gennis, Georgios
Gourdouparis, Marios
Dimas, Christos
Sotiriadis, Paul P.
A Low-Power Analog Integrated Implementation of the Support Vector Machine Algorithm with On-Chip Learning Tested on a Bearing Fault Application
title A Low-Power Analog Integrated Implementation of the Support Vector Machine Algorithm with On-Chip Learning Tested on a Bearing Fault Application
title_full A Low-Power Analog Integrated Implementation of the Support Vector Machine Algorithm with On-Chip Learning Tested on a Bearing Fault Application
title_fullStr A Low-Power Analog Integrated Implementation of the Support Vector Machine Algorithm with On-Chip Learning Tested on a Bearing Fault Application
title_full_unstemmed A Low-Power Analog Integrated Implementation of the Support Vector Machine Algorithm with On-Chip Learning Tested on a Bearing Fault Application
title_short A Low-Power Analog Integrated Implementation of the Support Vector Machine Algorithm with On-Chip Learning Tested on a Bearing Fault Application
title_sort low-power analog integrated implementation of the support vector machine algorithm with on-chip learning tested on a bearing fault application
topic Article
url https://www.ncbi.nlm.nih.gov/pmc/articles/PMC10145287/
https://www.ncbi.nlm.nih.gov/pubmed/37112319
http://dx.doi.org/10.3390/s23083978
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