A Low-Power Analog Integrated Implementation of the Support Vector Machine Algorithm with On-Chip Learning Tested on a Bearing Fault Application

A novel analog integrated implementation of a hardware-friendly support vector machine algorithm that can be a part of a classification system is presented in this work. The utilized architecture is capable of on-chip learning, making the overall circuit completely autonomous at the cost of power an...

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Detalles Bibliográficos
Autores principales: Alimisis, Vassilis, Gennis, Georgios, Gourdouparis, Marios, Dimas, Christos, Sotiriadis, Paul P.
Formato: Online Artículo Texto
Lenguaje:English
Publicado: MDPI 2023
Materias:
Article
Acceso en línea:https://www.ncbi.nlm.nih.gov/pmc/articles/PMC10145287/
https://www.ncbi.nlm.nih.gov/pubmed/37112319
http://dx.doi.org/10.3390/s23083978

Internet

https://www.ncbi.nlm.nih.gov/pmc/articles/PMC10145287/
https://www.ncbi.nlm.nih.gov/pubmed/37112319
http://dx.doi.org/10.3390/s23083978

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