High-Performance P- and N-Type SiGe/Si Strained Super-Lattice FinFET and CMOS Inverter: Comparison of Si and SiGe FinFET

This research presents the optimization and proposal of P- and N-type 3-stacked Si(0.8)Ge(0.2)/Si strained super-lattice FinFETs (SL FinFET) using Low-Pressure Chemical Vapor Deposition (LPCVD) epitaxy. Three device structures, Si FinFET, Si(0.8)Ge(0.2) FinFET, and Si(0.8)Ge(0.2)/Si SL FinFET, were comprehensively compared with HfO(2) = 4 nm/TiN = 80 nm. The strained effect was analyzed using Raman spectrum and X-ray diffraction reciprocal space mapping (RSM). The results show that Si(0.8)Ge(0.2)/Si SL FinFET exhibited the lowest average subthreshold slope (SS(avg)) of 88 mV/dec, the highest maximum transconductance (G(m, max)) of 375.2 μS/μm, and the highest ON–OFF current ratio (I(ON)/I(OFF)), approximately 10(6) at V(OV) = 0.5 V due to the strained effect. Furthermore, with the super-lattice FinFETs as complementary metal–oxide–semiconductor (CMOS) inverters, a maximum gain of 91 v/v was achieved by varying the supply voltage from 0.6 V to 1.2 V. The simulation of a Si(0.8)Ge(0.2)/Si super-lattice FinFET with the state of the art was also investigated. The proposed Si(0.8)Ge(0.2)/Si strained SL FinFET is fully compatible with the CMOS technology platform, showing promising flexibility for extending CMOS scaling.