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Performance of Active-Quenching SPAD Array Based on the Tri-State Gates of FPGA and Packaged with Bare Chip Stacking

The performance of an active-quenching single-photon avalanche diode (SPAD) array that is based on the tri-state gates of a field programmable gate array (FPGA) is presented. The array is implemented by stacking a bare 4 × 4 N-on-P SPAD array on a bare FPGA die, and the electrodes of the SPAD pixels...

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Autores principales: Liu, Liangliang, Lv, Wenxing, Liu, Jian, Zhang, Xingan, Liang, Kun, Yang, Ru, Han, Dejun
Formato: Online Artículo Texto
Lenguaje:English
Publicado: MDPI 2023
Materias:
Acceso en línea:https://www.ncbi.nlm.nih.gov/pmc/articles/PMC10181700/
https://www.ncbi.nlm.nih.gov/pubmed/37177518
http://dx.doi.org/10.3390/s23094314
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author Liu, Liangliang
Lv, Wenxing
Liu, Jian
Zhang, Xingan
Liang, Kun
Yang, Ru
Han, Dejun
author_facet Liu, Liangliang
Lv, Wenxing
Liu, Jian
Zhang, Xingan
Liang, Kun
Yang, Ru
Han, Dejun
author_sort Liu, Liangliang
collection PubMed
description The performance of an active-quenching single-photon avalanche diode (SPAD) array that is based on the tri-state gates of a field programmable gate array (FPGA) is presented. The array is implemented by stacking a bare 4 × 4 N-on-P SPAD array on a bare FPGA die, and the electrodes of the SPAD pixels and the I/O ports of the FPGA are connected through wire bonding within the same package. The active quenching action on each SPAD pixel is performed by using the properties of the tri-state gates of the FPGA. Digital signal processing, such as pulse counters, data encoders, and command interactions, is also performed by using the same FPGA. The breakdown voltage of the SPAD pixels, with an active area of 60 μm × 60 μm, is 47.2–48.0 V. When the device is reverse biased at a voltage of ~50.4 V, a response delay of ~50 ns, a dead time of 157 ns, a dark count rate of 2.44 kHz, and an afterpulsing probability of 6.9% are obtained. Its peak photon detection probability (PDP) reaches 17.0% at a peak wavelength of 760 nm and remains above 10% at 900 nm. This hybrid integrated SPAD array is reconfigurable and cost effective.
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spelling pubmed-101817002023-05-13 Performance of Active-Quenching SPAD Array Based on the Tri-State Gates of FPGA and Packaged with Bare Chip Stacking Liu, Liangliang Lv, Wenxing Liu, Jian Zhang, Xingan Liang, Kun Yang, Ru Han, Dejun Sensors (Basel) Article The performance of an active-quenching single-photon avalanche diode (SPAD) array that is based on the tri-state gates of a field programmable gate array (FPGA) is presented. The array is implemented by stacking a bare 4 × 4 N-on-P SPAD array on a bare FPGA die, and the electrodes of the SPAD pixels and the I/O ports of the FPGA are connected through wire bonding within the same package. The active quenching action on each SPAD pixel is performed by using the properties of the tri-state gates of the FPGA. Digital signal processing, such as pulse counters, data encoders, and command interactions, is also performed by using the same FPGA. The breakdown voltage of the SPAD pixels, with an active area of 60 μm × 60 μm, is 47.2–48.0 V. When the device is reverse biased at a voltage of ~50.4 V, a response delay of ~50 ns, a dead time of 157 ns, a dark count rate of 2.44 kHz, and an afterpulsing probability of 6.9% are obtained. Its peak photon detection probability (PDP) reaches 17.0% at a peak wavelength of 760 nm and remains above 10% at 900 nm. This hybrid integrated SPAD array is reconfigurable and cost effective. MDPI 2023-04-27 /pmc/articles/PMC10181700/ /pubmed/37177518 http://dx.doi.org/10.3390/s23094314 Text en © 2023 by the authors. https://creativecommons.org/licenses/by/4.0/Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https://creativecommons.org/licenses/by/4.0/).
spellingShingle Article
Liu, Liangliang
Lv, Wenxing
Liu, Jian
Zhang, Xingan
Liang, Kun
Yang, Ru
Han, Dejun
Performance of Active-Quenching SPAD Array Based on the Tri-State Gates of FPGA and Packaged with Bare Chip Stacking
title Performance of Active-Quenching SPAD Array Based on the Tri-State Gates of FPGA and Packaged with Bare Chip Stacking
title_full Performance of Active-Quenching SPAD Array Based on the Tri-State Gates of FPGA and Packaged with Bare Chip Stacking
title_fullStr Performance of Active-Quenching SPAD Array Based on the Tri-State Gates of FPGA and Packaged with Bare Chip Stacking
title_full_unstemmed Performance of Active-Quenching SPAD Array Based on the Tri-State Gates of FPGA and Packaged with Bare Chip Stacking
title_short Performance of Active-Quenching SPAD Array Based on the Tri-State Gates of FPGA and Packaged with Bare Chip Stacking
title_sort performance of active-quenching spad array based on the tri-state gates of fpga and packaged with bare chip stacking
topic Article
url https://www.ncbi.nlm.nih.gov/pmc/articles/PMC10181700/
https://www.ncbi.nlm.nih.gov/pubmed/37177518
http://dx.doi.org/10.3390/s23094314
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