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A reconfigurable binary/ternary logic conversion-in-memory based on drain-aligned floating-gate heterojunction transistors

A new type of heterojunction non-volatile memory transistor (H-MTR) has been developed, in which the negative transconductance (NTC) characteristics can be controlled systematically by a drain-aligned floating gate. In the H-MTR, a reliable transition between N-shaped transfer curves with distinct N...

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Autores principales: Lee, Chungryeol, Lee, Changhyeon, Lee, Seungmin, Choi, Junhwan, Yoo, Hocheon, Im, Sung Gap
Formato: Online Artículo Texto
Lenguaje:English
Publicado: Nature Publishing Group UK 2023
Materias:
Acceso en línea:https://www.ncbi.nlm.nih.gov/pmc/articles/PMC10290076/
https://www.ncbi.nlm.nih.gov/pubmed/37353504
http://dx.doi.org/10.1038/s41467-023-39394-5
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author Lee, Chungryeol
Lee, Changhyeon
Lee, Seungmin
Choi, Junhwan
Yoo, Hocheon
Im, Sung Gap
author_facet Lee, Chungryeol
Lee, Changhyeon
Lee, Seungmin
Choi, Junhwan
Yoo, Hocheon
Im, Sung Gap
author_sort Lee, Chungryeol
collection PubMed
description A new type of heterojunction non-volatile memory transistor (H-MTR) has been developed, in which the negative transconductance (NTC) characteristics can be controlled systematically by a drain-aligned floating gate. In the H-MTR, a reliable transition between N-shaped transfer curves with distinct NTC and monolithically current-increasing transfer curves without apparent NTC can be accomplished through programming operation. Based on the H-MTR, a binary/ternary reconfigurable logic inverter (R-inverter) has been successfully implemented, which showed an unprecedentedly high static noise margin of 85% for binary logic operation and 59% for ternary logic operation, as well as long-term stability and outstanding cycle endurance. Furthermore, a ternary/binary dynamic logic conversion-in-memory has been demonstrated using a serially-connected R-inverter chain. The ternary/binary dynamic logic conversion-in-memory could generate three different output logic sequences for the same input signal in three logic levels, which is a new logic computing method that has never been presented before.
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spelling pubmed-102900762023-06-25 A reconfigurable binary/ternary logic conversion-in-memory based on drain-aligned floating-gate heterojunction transistors Lee, Chungryeol Lee, Changhyeon Lee, Seungmin Choi, Junhwan Yoo, Hocheon Im, Sung Gap Nat Commun Article A new type of heterojunction non-volatile memory transistor (H-MTR) has been developed, in which the negative transconductance (NTC) characteristics can be controlled systematically by a drain-aligned floating gate. In the H-MTR, a reliable transition between N-shaped transfer curves with distinct NTC and monolithically current-increasing transfer curves without apparent NTC can be accomplished through programming operation. Based on the H-MTR, a binary/ternary reconfigurable logic inverter (R-inverter) has been successfully implemented, which showed an unprecedentedly high static noise margin of 85% for binary logic operation and 59% for ternary logic operation, as well as long-term stability and outstanding cycle endurance. Furthermore, a ternary/binary dynamic logic conversion-in-memory has been demonstrated using a serially-connected R-inverter chain. The ternary/binary dynamic logic conversion-in-memory could generate three different output logic sequences for the same input signal in three logic levels, which is a new logic computing method that has never been presented before. Nature Publishing Group UK 2023-06-23 /pmc/articles/PMC10290076/ /pubmed/37353504 http://dx.doi.org/10.1038/s41467-023-39394-5 Text en © The Author(s) 2023 https://creativecommons.org/licenses/by/4.0/Open Access This article is licensed under a Creative Commons Attribution 4.0 International License, which permits use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license, and indicate if changes were made. The images or other third party material in this article are included in the article’s Creative Commons license, unless indicated otherwise in a credit line to the material. If material is not included in the article’s Creative Commons license and your intended use is not permitted by statutory regulation or exceeds the permitted use, you will need to obtain permission directly from the copyright holder. To view a copy of this license, visit http://creativecommons.org/licenses/by/4.0/ (https://creativecommons.org/licenses/by/4.0/) .
spellingShingle Article
Lee, Chungryeol
Lee, Changhyeon
Lee, Seungmin
Choi, Junhwan
Yoo, Hocheon
Im, Sung Gap
A reconfigurable binary/ternary logic conversion-in-memory based on drain-aligned floating-gate heterojunction transistors
title A reconfigurable binary/ternary logic conversion-in-memory based on drain-aligned floating-gate heterojunction transistors
title_full A reconfigurable binary/ternary logic conversion-in-memory based on drain-aligned floating-gate heterojunction transistors
title_fullStr A reconfigurable binary/ternary logic conversion-in-memory based on drain-aligned floating-gate heterojunction transistors
title_full_unstemmed A reconfigurable binary/ternary logic conversion-in-memory based on drain-aligned floating-gate heterojunction transistors
title_short A reconfigurable binary/ternary logic conversion-in-memory based on drain-aligned floating-gate heterojunction transistors
title_sort reconfigurable binary/ternary logic conversion-in-memory based on drain-aligned floating-gate heterojunction transistors
topic Article
url https://www.ncbi.nlm.nih.gov/pmc/articles/PMC10290076/
https://www.ncbi.nlm.nih.gov/pubmed/37353504
http://dx.doi.org/10.1038/s41467-023-39394-5
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