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A 12-Bit 2 GS/s Single-Channel High Linearity Pipelined ADC in 40 nm CMOS

This paper presents a single-channel 12-bit, 2 GS/s pipelined analog-to-digital converter (ADC) for wideband sampling receivers. The design adopts a novel source follower input buffer with multiple feedback loops to improve sample linearity and extend bandwidth. Additionally, an improved two stages...

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Detalles Bibliográficos
Autores principales:	Wu, Feitong, Guo, Xuan, Jia, Hanbo, Wu, Xiuheng, Li, Zeyu, He, Ben, Wu, Danyu, Liu, Xinyu
Formato:	Online Artículo Texto
Lenguaje:	English
Publicado:	MDPI 2023
Materias:	Article
Acceso en línea:	https://www.ncbi.nlm.nih.gov/pmc/articles/PMC10385724/ https://www.ncbi.nlm.nih.gov/pubmed/37512602 http://dx.doi.org/10.3390/mi14071291

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