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Inductive line tunneling FET using epitaxial tunnel layer with Ge-source and charge enhancement insulation
In this paper, we propose an inductive line tunneling FET using Epitaxial Tunnel Layer with Ge-Source and Charge Enhancement Insulation (CEI ETL GS-iTFET). The CEI ETL GS-iTFET allows full overlap between the gate and source regions, thereby enhancing the line tunneling. In addition, a germanium lay...
| Autores principales: | , |
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| Formato: | Online Artículo Texto |
| Lenguaje: | English |
| Publicado: |
Springer US
2023
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| Materias: | |
| Acceso en línea: | https://www.ncbi.nlm.nih.gov/pmc/articles/PMC10404213/ https://www.ncbi.nlm.nih.gov/pubmed/37542560 http://dx.doi.org/10.1186/s11671-023-03878-6 |