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Al(2)O(3) Layers Grown by Atomic Layer Deposition as Gate Insulator in 3C-SiC MOS Devices
Metal-oxide-semiconductor (MOS) capacitors with Al(2)O(3) as a gate insulator are fabricated on cubic silicon carbide (3C-SiC). Al(2)O(3) is deposited both by thermal and plasma-enhanced Atomic Layer Deposition (ALD) on a thermally grown 5 nm SiO(2) interlayer to improve the ALD nucleation and guara...
Autores principales: | , , , , , , , , , |
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Formato: | Online Artículo Texto |
Lenguaje: | English |
Publicado: |
MDPI
2023
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Materias: | |
Acceso en línea: | https://www.ncbi.nlm.nih.gov/pmc/articles/PMC10456437/ https://www.ncbi.nlm.nih.gov/pubmed/37629929 http://dx.doi.org/10.3390/ma16165638 |
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author | Schilirò, Emanuela Fiorenza, Patrick Lo Nigro, Raffaella Galizia, Bruno Greco, Giuseppe Di Franco, Salvatore Bongiorno, Corrado La Via, Francesco Giannazzo, Filippo Roccaforte, Fabrizio |
author_facet | Schilirò, Emanuela Fiorenza, Patrick Lo Nigro, Raffaella Galizia, Bruno Greco, Giuseppe Di Franco, Salvatore Bongiorno, Corrado La Via, Francesco Giannazzo, Filippo Roccaforte, Fabrizio |
author_sort | Schilirò, Emanuela |
collection | PubMed |
description | Metal-oxide-semiconductor (MOS) capacitors with Al(2)O(3) as a gate insulator are fabricated on cubic silicon carbide (3C-SiC). Al(2)O(3) is deposited both by thermal and plasma-enhanced Atomic Layer Deposition (ALD) on a thermally grown 5 nm SiO(2) interlayer to improve the ALD nucleation and guarantee a better band offset with the SiC. The deposited Al(2)O(3)/SiO(2) stacks show lower negative shifts of the flat band voltage V(FB) (in the range of about −3 V) compared with the conventional single SiO(2) layer (in the range of −9 V). This lower negative shift is due to the combined effect of the Al(2)O(3) higher permittivity (ε = 8) and to the reduced amount of carbon defects generated during the short thermal oxidation process for the thin SiO(2). Moreover, the comparison between thermal and plasma-enhanced ALD suggests that this latter approach produces Al(2)O(3) layers possessing better insulating behavior in terms of distribution of the leakage current breakdown. In fact, despite both possessing a breakdown voltage of 26 V, the T-ALD Al(2)O(3) sample is characterised by a higher current density starting from 15 V. This can be attributable to the slightly inferior quality (in terms of density and defects) of Al(2)O(3) obtained by the thermal approach and, which also explains its non-uniform dC/dV distribution arising by SCM maps. |
format | Online Article Text |
id | pubmed-10456437 |
institution | National Center for Biotechnology Information |
language | English |
publishDate | 2023 |
publisher | MDPI |
record_format | MEDLINE/PubMed |
spelling | pubmed-104564372023-08-26 Al(2)O(3) Layers Grown by Atomic Layer Deposition as Gate Insulator in 3C-SiC MOS Devices Schilirò, Emanuela Fiorenza, Patrick Lo Nigro, Raffaella Galizia, Bruno Greco, Giuseppe Di Franco, Salvatore Bongiorno, Corrado La Via, Francesco Giannazzo, Filippo Roccaforte, Fabrizio Materials (Basel) Article Metal-oxide-semiconductor (MOS) capacitors with Al(2)O(3) as a gate insulator are fabricated on cubic silicon carbide (3C-SiC). Al(2)O(3) is deposited both by thermal and plasma-enhanced Atomic Layer Deposition (ALD) on a thermally grown 5 nm SiO(2) interlayer to improve the ALD nucleation and guarantee a better band offset with the SiC. The deposited Al(2)O(3)/SiO(2) stacks show lower negative shifts of the flat band voltage V(FB) (in the range of about −3 V) compared with the conventional single SiO(2) layer (in the range of −9 V). This lower negative shift is due to the combined effect of the Al(2)O(3) higher permittivity (ε = 8) and to the reduced amount of carbon defects generated during the short thermal oxidation process for the thin SiO(2). Moreover, the comparison between thermal and plasma-enhanced ALD suggests that this latter approach produces Al(2)O(3) layers possessing better insulating behavior in terms of distribution of the leakage current breakdown. In fact, despite both possessing a breakdown voltage of 26 V, the T-ALD Al(2)O(3) sample is characterised by a higher current density starting from 15 V. This can be attributable to the slightly inferior quality (in terms of density and defects) of Al(2)O(3) obtained by the thermal approach and, which also explains its non-uniform dC/dV distribution arising by SCM maps. MDPI 2023-08-15 /pmc/articles/PMC10456437/ /pubmed/37629929 http://dx.doi.org/10.3390/ma16165638 Text en © 2023 by the authors. https://creativecommons.org/licenses/by/4.0/Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https://creativecommons.org/licenses/by/4.0/). |
spellingShingle | Article Schilirò, Emanuela Fiorenza, Patrick Lo Nigro, Raffaella Galizia, Bruno Greco, Giuseppe Di Franco, Salvatore Bongiorno, Corrado La Via, Francesco Giannazzo, Filippo Roccaforte, Fabrizio Al(2)O(3) Layers Grown by Atomic Layer Deposition as Gate Insulator in 3C-SiC MOS Devices |
title | Al(2)O(3) Layers Grown by Atomic Layer Deposition as Gate Insulator in 3C-SiC MOS Devices |
title_full | Al(2)O(3) Layers Grown by Atomic Layer Deposition as Gate Insulator in 3C-SiC MOS Devices |
title_fullStr | Al(2)O(3) Layers Grown by Atomic Layer Deposition as Gate Insulator in 3C-SiC MOS Devices |
title_full_unstemmed | Al(2)O(3) Layers Grown by Atomic Layer Deposition as Gate Insulator in 3C-SiC MOS Devices |
title_short | Al(2)O(3) Layers Grown by Atomic Layer Deposition as Gate Insulator in 3C-SiC MOS Devices |
title_sort | al(2)o(3) layers grown by atomic layer deposition as gate insulator in 3c-sic mos devices |
topic | Article |
url | https://www.ncbi.nlm.nih.gov/pmc/articles/PMC10456437/ https://www.ncbi.nlm.nih.gov/pubmed/37629929 http://dx.doi.org/10.3390/ma16165638 |
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