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The Design of a Dynamic Configurable Packet Parser Based on FPGA
To meet the evolving demands of programmable networks and address the limitations of traditional fixed-type protocol parsers, we propose a dynamic and configurable low-latency parser implemented on an FPGA. The architecture consists of three protocol analysis modules and a TCAM-SRAM. Latency is redu...
| Autores principales: | , |
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| Formato: | Online Artículo Texto |
| Lenguaje: | English |
| Publicado: |
MDPI
2023
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| Acceso en línea: | https://www.ncbi.nlm.nih.gov/pmc/articles/PMC10456924/ https://www.ncbi.nlm.nih.gov/pubmed/37630096 http://dx.doi.org/10.3390/mi14081560 |