The Impact of Ambient Temperature on Electrothermal Characteristics in Stacked Nanosheet Transistors with Multiple Lateral Stacks

With characteristic size scaling down to the nanoscale range, the confined geometry exacerbates the self-heating effect (SHE) in nanoscale devices. In this paper, the impact of ambient temperature (T(amb)) on the SHE in stacked nanosheet transistors is investigated. As the number of lateral stacks (N(stack)) increases, the nanoscale devices show more severe thermal crosstalk issues, and the current performance between n- and p-type nanoscale transistors exhibits different degradation trends. To compare the effect of different T(amb) ranges, the temperature coefficients of current per stack and threshold voltage are analyzed. As the N(stack) increases from 4 to 32, it is verified that the zero-temperature coefficient bias point (V(ZTC)) decreases significantly in p-type nanoscale devices when T(amb) is above room temperature. This can be explained by the enhanced thermal crosstalk. Then, the gate length-dependent electrothermal characteristics with different N(stack)s are investigated at various T(amb)s. To explore the origin of drain current variation, the temperature-dependent backscattering model is utilized to explain the variation. At last, the simulation results verify the impact of T(amb) on the SHE. The study provides an effective design guide for stacked nanosheet transistors when considering multiple stacks in circuit applications.