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Efficient k-Winner-Take-All Competitive Learning Hardware Architecture for On-Chip Learning

A novel k-winners-take-all (k-WTA) competitive learning (CL) hardware architecture is presented for on-chip learning in this paper. The architecture is based on an efficient pipeline allowing k-WTA competition processes associated with different training vectors to be performed concurrently. The pip...

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Detalles Bibliográficos
Autores principales: Ou, Chien-Min, Li, Hui-Ya, Hwang, Wen-Jyi
Formato: Online Artículo Texto
Lenguaje:English
Publicado: Molecular Diversity Preservation International (MDPI) 2012
Materias:
Acceso en línea:https://www.ncbi.nlm.nih.gov/pmc/articles/PMC3478803/
http://dx.doi.org/10.3390/s120911661
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author Ou, Chien-Min
Li, Hui-Ya
Hwang, Wen-Jyi
author_facet Ou, Chien-Min
Li, Hui-Ya
Hwang, Wen-Jyi
author_sort Ou, Chien-Min
collection PubMed
description A novel k-winners-take-all (k-WTA) competitive learning (CL) hardware architecture is presented for on-chip learning in this paper. The architecture is based on an efficient pipeline allowing k-WTA competition processes associated with different training vectors to be performed concurrently. The pipeline architecture employs a novel codeword swapping scheme so that neurons failing the competition for a training vector are immediately available for the competitions for the subsequent training vectors. The architecture is implemented by the field programmable gate array (FPGA). It is used as a hardware accelerator in a system on programmable chip (SOPC) for realtime on-chip learning. Experimental results show that the SOPC has significantly lower training time than that of other k-WTA CL counterparts operating with or without hardware support.
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spelling pubmed-34788032012-10-30 Efficient k-Winner-Take-All Competitive Learning Hardware Architecture for On-Chip Learning Ou, Chien-Min Li, Hui-Ya Hwang, Wen-Jyi Sensors (Basel) Article A novel k-winners-take-all (k-WTA) competitive learning (CL) hardware architecture is presented for on-chip learning in this paper. The architecture is based on an efficient pipeline allowing k-WTA competition processes associated with different training vectors to be performed concurrently. The pipeline architecture employs a novel codeword swapping scheme so that neurons failing the competition for a training vector are immediately available for the competitions for the subsequent training vectors. The architecture is implemented by the field programmable gate array (FPGA). It is used as a hardware accelerator in a system on programmable chip (SOPC) for realtime on-chip learning. Experimental results show that the SOPC has significantly lower training time than that of other k-WTA CL counterparts operating with or without hardware support. Molecular Diversity Preservation International (MDPI) 2012-08-27 /pmc/articles/PMC3478803/ http://dx.doi.org/10.3390/s120911661 Text en © 2012 by the authors; licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution license (http://creativecommons.org/licenses/by/3.0/. (http://creativecommons.org/licenses/by/3.0/) )
spellingShingle Article
Ou, Chien-Min
Li, Hui-Ya
Hwang, Wen-Jyi
Efficient k-Winner-Take-All Competitive Learning Hardware Architecture for On-Chip Learning
title Efficient k-Winner-Take-All Competitive Learning Hardware Architecture for On-Chip Learning
title_full Efficient k-Winner-Take-All Competitive Learning Hardware Architecture for On-Chip Learning
title_fullStr Efficient k-Winner-Take-All Competitive Learning Hardware Architecture for On-Chip Learning
title_full_unstemmed Efficient k-Winner-Take-All Competitive Learning Hardware Architecture for On-Chip Learning
title_short Efficient k-Winner-Take-All Competitive Learning Hardware Architecture for On-Chip Learning
title_sort efficient k-winner-take-all competitive learning hardware architecture for on-chip learning
topic Article
url https://www.ncbi.nlm.nih.gov/pmc/articles/PMC3478803/
http://dx.doi.org/10.3390/s120911661
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