Ag/GeS(x)/Pt-based complementary resistive switches for hybrid CMOS/Nanoelectronic logic and memory architectures

Complementary resistive switches based on two anti-serially connected Ag/GeS(x)/Pt devices were studied. The main focus was placed on the pulse mode properties as typically required in memory and logic applications. A self-designed measurement setup was applied to access each CRS part-cell individually. Our findings reveal the existence of two distinct read voltage regimes enabling both spike read as well as level read approaches. Furthermore, we experimentally verified the theoretically predicted kinetic properties in terms of pulse height vs. switching time relationship. The results obtained by this alternative approach allow a significant improvement of the basic understanding of the interplay between the two part-cells in a complementary resistive switch configuration. Furthermore, from these observations we can deduce a simplified write voltage scheme which is applicable for the considered type of memory cell.