Reflection Reduction on DDR3 High-Speed Bus by Improved PSO

The signal integrity of the circuit, as one of the important design issues in high-speed digital system, is usually seriously affected by the signal reflection due to impedance mismatch in the DDR3 bus. In this paper, a novel optimization method is proposed to optimize impedance mismatch and reduce...

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Detalles Bibliográficos
Autores principales: Li, Huiyong, Jiang, Hongxu, Li, Bo, Duan, Miyi
Formato: Online Artículo Texto
Lenguaje:English
Publicado: Hindawi Publishing Corporation 2014
Materias:
Research Article
Acceso en línea:https://www.ncbi.nlm.nih.gov/pmc/articles/PMC3977529/
https://www.ncbi.nlm.nih.gov/pubmed/24778582
http://dx.doi.org/10.1155/2014/257972

Internet

https://www.ncbi.nlm.nih.gov/pmc/articles/PMC3977529/
https://www.ncbi.nlm.nih.gov/pubmed/24778582
http://dx.doi.org/10.1155/2014/257972

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