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Enabling an Integrated Rate-temporal Learning Scheme on Memristor

Learning scheme is the key to the utilization of spike-based computation and the emulation of neural/synaptic behaviors toward realization of cognition. The biological observations reveal an integrated spike time- and spike rate-dependent plasticity as a function of presynaptic firing frequency. How...

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Autores principales: He, Wei, Huang, Kejie, Ning, Ning, Ramanathan, Kiruthika, Li, Guoqi, Jiang, Yu, Sze, JiaYin, Shi, Luping, Zhao, Rong, Pei, Jing
Formato: Online Artículo Texto
Lenguaje:English
Publicado: Nature Publishing Group 2014
Materias:
Acceso en línea:https://www.ncbi.nlm.nih.gov/pmc/articles/PMC3996481/
https://www.ncbi.nlm.nih.gov/pubmed/24755608
http://dx.doi.org/10.1038/srep04755
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author He, Wei
Huang, Kejie
Ning, Ning
Ramanathan, Kiruthika
Li, Guoqi
Jiang, Yu
Sze, JiaYin
Shi, Luping
Zhao, Rong
Pei, Jing
author_facet He, Wei
Huang, Kejie
Ning, Ning
Ramanathan, Kiruthika
Li, Guoqi
Jiang, Yu
Sze, JiaYin
Shi, Luping
Zhao, Rong
Pei, Jing
author_sort He, Wei
collection PubMed
description Learning scheme is the key to the utilization of spike-based computation and the emulation of neural/synaptic behaviors toward realization of cognition. The biological observations reveal an integrated spike time- and spike rate-dependent plasticity as a function of presynaptic firing frequency. However, this integrated rate-temporal learning scheme has not been realized on any nano devices. In this paper, such scheme is successfully demonstrated on a memristor. Great robustness against the spiking rate fluctuation is achieved by waveform engineering with the aid of good analog properties exhibited by the iron oxide-based memristor. The spike-time-dependence plasticity (STDP) occurs at moderate presynaptic firing frequencies and spike-rate-dependence plasticity (SRDP) dominates other regions. This demonstration provides a novel approach in neural coding implementation, which facilitates the development of bio-inspired computing systems.
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spelling pubmed-39964812014-04-24 Enabling an Integrated Rate-temporal Learning Scheme on Memristor He, Wei Huang, Kejie Ning, Ning Ramanathan, Kiruthika Li, Guoqi Jiang, Yu Sze, JiaYin Shi, Luping Zhao, Rong Pei, Jing Sci Rep Article Learning scheme is the key to the utilization of spike-based computation and the emulation of neural/synaptic behaviors toward realization of cognition. The biological observations reveal an integrated spike time- and spike rate-dependent plasticity as a function of presynaptic firing frequency. However, this integrated rate-temporal learning scheme has not been realized on any nano devices. In this paper, such scheme is successfully demonstrated on a memristor. Great robustness against the spiking rate fluctuation is achieved by waveform engineering with the aid of good analog properties exhibited by the iron oxide-based memristor. The spike-time-dependence plasticity (STDP) occurs at moderate presynaptic firing frequencies and spike-rate-dependence plasticity (SRDP) dominates other regions. This demonstration provides a novel approach in neural coding implementation, which facilitates the development of bio-inspired computing systems. Nature Publishing Group 2014-04-23 /pmc/articles/PMC3996481/ /pubmed/24755608 http://dx.doi.org/10.1038/srep04755 Text en Copyright © 2014, Macmillan Publishers Limited. All rights reserved http://creativecommons.org/licenses/by-nc-nd/3.0/ This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivs 3.0 Unported License. The images in this article are included in the article's Creative Commons license, unless indicated otherwise in the image credit; if the image is not included under the Creative Commons license, users will need to obtain permission from the license holder in order to reproduce the image. To view a copy of this license, visit http://creativecommons.org/licenses/by-nc-nd/3.0/
spellingShingle Article
He, Wei
Huang, Kejie
Ning, Ning
Ramanathan, Kiruthika
Li, Guoqi
Jiang, Yu
Sze, JiaYin
Shi, Luping
Zhao, Rong
Pei, Jing
Enabling an Integrated Rate-temporal Learning Scheme on Memristor
title Enabling an Integrated Rate-temporal Learning Scheme on Memristor
title_full Enabling an Integrated Rate-temporal Learning Scheme on Memristor
title_fullStr Enabling an Integrated Rate-temporal Learning Scheme on Memristor
title_full_unstemmed Enabling an Integrated Rate-temporal Learning Scheme on Memristor
title_short Enabling an Integrated Rate-temporal Learning Scheme on Memristor
title_sort enabling an integrated rate-temporal learning scheme on memristor
topic Article
url https://www.ncbi.nlm.nih.gov/pmc/articles/PMC3996481/
https://www.ncbi.nlm.nih.gov/pubmed/24755608
http://dx.doi.org/10.1038/srep04755
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