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Hardware Implementation of 32-Bit High-Speed Direct Digital Frequency Synthesizer
The design and implementation of a high-speed direct digital frequency synthesizer are presented. A modified Brent-Kung parallel adder is combined with pipelining technique to improve the speed of the system. A gated clock technique is proposed to reduce the number of registers in the phase accumula...
Autores principales: | Ibrahim, Salah Hasan, Ali, Sawal Hamid Md., Islam, Md. Shabiul |
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Formato: | Online Artículo Texto |
Lenguaje: | English |
Publicado: |
Hindawi Publishing Corporation
2014
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Materias: | |
Acceso en línea: | https://www.ncbi.nlm.nih.gov/pmc/articles/PMC4060586/ https://www.ncbi.nlm.nih.gov/pubmed/24991635 http://dx.doi.org/10.1155/2014/131568 |
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