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Graphene/Si CMOS Hybrid Hall Integrated Circuits

Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this...

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Autores principales: Huang, Le, Xu, Huilong, Zhang, Zhiyong, Chen, Chengying, Jiang, Jianhua, Ma, Xiaomeng, Chen, Bingyan, Li, Zishen, Zhong, Hua, Peng, Lian-Mao
Formato: Online Artículo Texto
Lenguaje:English
Publicado: Nature Publishing Group 2014
Materias:
Acceso en línea:https://www.ncbi.nlm.nih.gov/pmc/articles/PMC4083279/
https://www.ncbi.nlm.nih.gov/pubmed/24998222
http://dx.doi.org/10.1038/srep05548
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author Huang, Le
Xu, Huilong
Zhang, Zhiyong
Chen, Chengying
Jiang, Jianhua
Ma, Xiaomeng
Chen, Bingyan
Li, Zishen
Zhong, Hua
Peng, Lian-Mao
author_facet Huang, Le
Xu, Huilong
Zhang, Zhiyong
Chen, Chengying
Jiang, Jianhua
Ma, Xiaomeng
Chen, Bingyan
Li, Zishen
Zhong, Hua
Peng, Lian-Mao
author_sort Huang, Le
collection PubMed
description Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18 um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process.
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spelling pubmed-40832792014-07-08 Graphene/Si CMOS Hybrid Hall Integrated Circuits Huang, Le Xu, Huilong Zhang, Zhiyong Chen, Chengying Jiang, Jianhua Ma, Xiaomeng Chen, Bingyan Li, Zishen Zhong, Hua Peng, Lian-Mao Sci Rep Article Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18 um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process. Nature Publishing Group 2014-07-07 /pmc/articles/PMC4083279/ /pubmed/24998222 http://dx.doi.org/10.1038/srep05548 Text en Copyright © 2014, Macmillan Publishers Limited. All rights reserved http://creativecommons.org/licenses/by-nc-nd/4.0/ This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivs 4.0 International License. The images or other third party material in this article are included in the article's Creative Commons license, unless indicated otherwise in the credit line; if the material is not included under the Creative Commons license, users will need to obtain permission from the license holder in order to reproduce the material. To view a copy of this license, visit http://creativecommons.org/licenses/by-nc-nd/4.0/
spellingShingle Article
Huang, Le
Xu, Huilong
Zhang, Zhiyong
Chen, Chengying
Jiang, Jianhua
Ma, Xiaomeng
Chen, Bingyan
Li, Zishen
Zhong, Hua
Peng, Lian-Mao
Graphene/Si CMOS Hybrid Hall Integrated Circuits
title Graphene/Si CMOS Hybrid Hall Integrated Circuits
title_full Graphene/Si CMOS Hybrid Hall Integrated Circuits
title_fullStr Graphene/Si CMOS Hybrid Hall Integrated Circuits
title_full_unstemmed Graphene/Si CMOS Hybrid Hall Integrated Circuits
title_short Graphene/Si CMOS Hybrid Hall Integrated Circuits
title_sort graphene/si cmos hybrid hall integrated circuits
topic Article
url https://www.ncbi.nlm.nih.gov/pmc/articles/PMC4083279/
https://www.ncbi.nlm.nih.gov/pubmed/24998222
http://dx.doi.org/10.1038/srep05548
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