2.4 GHz CMOS Power Amplifier with Mode-Locking Structure to Enhance Gain

We propose a mode-locking method optimized for the cascode structure of an RF CMOS power amplifier. To maximize the advantage of the typical mode-locking method in the cascode structure, the input of the cross-coupled transistor is modified from that of a typical mode-locking structure. To prove the...

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Detalles Bibliográficos
Autores principales: Lee, Changhyun, Park, Changkun
Formato: Online Artículo Texto
Lenguaje:English
Publicado: Hindawi Publishing Corporation 2014
Materias:
Research Article
Acceso en línea:https://www.ncbi.nlm.nih.gov/pmc/articles/PMC4087256/
https://www.ncbi.nlm.nih.gov/pubmed/25045755
http://dx.doi.org/10.1155/2014/967181
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author Lee, Changhyun
Park, Changkun
author_facet Lee, Changhyun
Park, Changkun
author_sort Lee, Changhyun
collection PubMed
description We propose a mode-locking method optimized for the cascode structure of an RF CMOS power amplifier. To maximize the advantage of the typical mode-locking method in the cascode structure, the input of the cross-coupled transistor is modified from that of a typical mode-locking structure. To prove the feasibility of the proposed structure, we designed a 2.4 GHz CMOS power amplifier with a 0.18 μm RFCMOS process for polar transmitter applications. The measured power added efficiency is 34.9%, while the saturated output power is 23.32 dBm. The designed chip size is 1.4 × 0.6 mm(2).
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spelling pubmed-40872562014-07-20 2.4 GHz CMOS Power Amplifier with Mode-Locking Structure to Enhance Gain Lee, Changhyun Park, Changkun ScientificWorldJournal Research Article We propose a mode-locking method optimized for the cascode structure of an RF CMOS power amplifier. To maximize the advantage of the typical mode-locking method in the cascode structure, the input of the cross-coupled transistor is modified from that of a typical mode-locking structure. To prove the feasibility of the proposed structure, we designed a 2.4 GHz CMOS power amplifier with a 0.18 μm RFCMOS process for polar transmitter applications. The measured power added efficiency is 34.9%, while the saturated output power is 23.32 dBm. The designed chip size is 1.4 × 0.6 mm(2). Hindawi Publishing Corporation 2014 2014-06-17 /pmc/articles/PMC4087256/ /pubmed/25045755 http://dx.doi.org/10.1155/2014/967181 Text en Copyright © 2014 C. Lee and C. Park. https://creativecommons.org/licenses/by/3.0/ This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
spellingShingle Research Article
Lee, Changhyun
Park, Changkun
2.4 GHz CMOS Power Amplifier with Mode-Locking Structure to Enhance Gain
title 2.4 GHz CMOS Power Amplifier with Mode-Locking Structure to Enhance Gain
title_full 2.4 GHz CMOS Power Amplifier with Mode-Locking Structure to Enhance Gain
title_fullStr 2.4 GHz CMOS Power Amplifier with Mode-Locking Structure to Enhance Gain
title_full_unstemmed 2.4 GHz CMOS Power Amplifier with Mode-Locking Structure to Enhance Gain
title_short 2.4 GHz CMOS Power Amplifier with Mode-Locking Structure to Enhance Gain
title_sort 2.4 ghz cmos power amplifier with mode-locking structure to enhance gain
topic Research Article
url https://www.ncbi.nlm.nih.gov/pmc/articles/PMC4087256/
https://www.ncbi.nlm.nih.gov/pubmed/25045755
http://dx.doi.org/10.1155/2014/967181
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