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Effects of Gate Stack Structural and Process Defectivity on High-k Dielectric Dependence of NBTI Reliability in 32 nm Technology Node PMOSFETs

We present a simulation study on negative bias temperature instability (NBTI) induced hole trapping in E′ center defects, which leads to depassivation of interface trap precursor in different geometrical structures of high-k PMOSFET gate stacks using the two-stage NBTI model. The resulting degradati...

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Autores principales: Hussin, H., Soin, N., Bukhori, M. F., Wan Muhamad Hatta, S., Abdul Wahab, Y.
Formato: Online Artículo Texto
Lenguaje:English
Publicado: Hindawi Publishing Corporation 2014
Materias:
Acceso en línea:https://www.ncbi.nlm.nih.gov/pmc/articles/PMC4151535/
https://www.ncbi.nlm.nih.gov/pubmed/25221784
http://dx.doi.org/10.1155/2014/490829
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author Hussin, H.
Soin, N.
Bukhori, M. F.
Wan Muhamad Hatta, S.
Abdul Wahab, Y.
author_facet Hussin, H.
Soin, N.
Bukhori, M. F.
Wan Muhamad Hatta, S.
Abdul Wahab, Y.
author_sort Hussin, H.
collection PubMed
description We present a simulation study on negative bias temperature instability (NBTI) induced hole trapping in E′ center defects, which leads to depassivation of interface trap precursor in different geometrical structures of high-k PMOSFET gate stacks using the two-stage NBTI model. The resulting degradation is characterized based on the time evolution of the interface and hole trap densities, as well as the resulting threshold voltage shift. By varying the physical thicknesses of the interface silicon dioxide (SiO(2)) and hafnium oxide (HfO(2)) layers, we investigate how the variation in thickness affects hole trapping/detrapping at different stress temperatures. The results suggest that the degradations are highly dependent on the physical gate stack parameters for a given stress voltage and temperature. The degradation is more pronounced by 5% when the thicknesses of HfO(2) are increased but is reduced by 11% when the SiO(2) interface layer thickness is increased during lower stress voltage. However, at higher stress voltage, greater degradation is observed for a thicker SiO(2) interface layer. In addition, the existence of different stress temperatures at which the degradation behavior differs implies that the hole trapping/detrapping event is thermally activated.
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spelling pubmed-41515352014-09-14 Effects of Gate Stack Structural and Process Defectivity on High-k Dielectric Dependence of NBTI Reliability in 32 nm Technology Node PMOSFETs Hussin, H. Soin, N. Bukhori, M. F. Wan Muhamad Hatta, S. Abdul Wahab, Y. ScientificWorldJournal Research Article We present a simulation study on negative bias temperature instability (NBTI) induced hole trapping in E′ center defects, which leads to depassivation of interface trap precursor in different geometrical structures of high-k PMOSFET gate stacks using the two-stage NBTI model. The resulting degradation is characterized based on the time evolution of the interface and hole trap densities, as well as the resulting threshold voltage shift. By varying the physical thicknesses of the interface silicon dioxide (SiO(2)) and hafnium oxide (HfO(2)) layers, we investigate how the variation in thickness affects hole trapping/detrapping at different stress temperatures. The results suggest that the degradations are highly dependent on the physical gate stack parameters for a given stress voltage and temperature. The degradation is more pronounced by 5% when the thicknesses of HfO(2) are increased but is reduced by 11% when the SiO(2) interface layer thickness is increased during lower stress voltage. However, at higher stress voltage, greater degradation is observed for a thicker SiO(2) interface layer. In addition, the existence of different stress temperatures at which the degradation behavior differs implies that the hole trapping/detrapping event is thermally activated. Hindawi Publishing Corporation 2014 2014-08-17 /pmc/articles/PMC4151535/ /pubmed/25221784 http://dx.doi.org/10.1155/2014/490829 Text en Copyright © 2014 H. Hussin et al. https://creativecommons.org/licenses/by/3.0/ This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
spellingShingle Research Article
Hussin, H.
Soin, N.
Bukhori, M. F.
Wan Muhamad Hatta, S.
Abdul Wahab, Y.
Effects of Gate Stack Structural and Process Defectivity on High-k Dielectric Dependence of NBTI Reliability in 32 nm Technology Node PMOSFETs
title Effects of Gate Stack Structural and Process Defectivity on High-k Dielectric Dependence of NBTI Reliability in 32 nm Technology Node PMOSFETs
title_full Effects of Gate Stack Structural and Process Defectivity on High-k Dielectric Dependence of NBTI Reliability in 32 nm Technology Node PMOSFETs
title_fullStr Effects of Gate Stack Structural and Process Defectivity on High-k Dielectric Dependence of NBTI Reliability in 32 nm Technology Node PMOSFETs
title_full_unstemmed Effects of Gate Stack Structural and Process Defectivity on High-k Dielectric Dependence of NBTI Reliability in 32 nm Technology Node PMOSFETs
title_short Effects of Gate Stack Structural and Process Defectivity on High-k Dielectric Dependence of NBTI Reliability in 32 nm Technology Node PMOSFETs
title_sort effects of gate stack structural and process defectivity on high-k dielectric dependence of nbti reliability in 32 nm technology node pmosfets
topic Research Article
url https://www.ncbi.nlm.nih.gov/pmc/articles/PMC4151535/
https://www.ncbi.nlm.nih.gov/pubmed/25221784
http://dx.doi.org/10.1155/2014/490829
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