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Effects of Gate Stack Structural and Process Defectivity on High-k Dielectric Dependence of NBTI Reliability in 32 nm Technology Node PMOSFETs

We present a simulation study on negative bias temperature instability (NBTI) induced hole trapping in E′ center defects, which leads to depassivation of interface trap precursor in different geometrical structures of high-k PMOSFET gate stacks using the two-stage NBTI model. The resulting degradati...

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Detalles Bibliográficos
Autores principales:	Hussin, H., Soin, N., Bukhori, M. F., Wan Muhamad Hatta, S., Abdul Wahab, Y.
Formato:	Online Artículo Texto
Lenguaje:	English
Publicado:	Hindawi Publishing Corporation 2014
Materias:	Research Article
Acceso en línea:	https://www.ncbi.nlm.nih.gov/pmc/articles/PMC4151535/ https://www.ncbi.nlm.nih.gov/pubmed/25221784 http://dx.doi.org/10.1155/2014/490829

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