Parallel Fixed Point Implementation of a Radial Basis Function Network in an FPGA

This paper proposes a parallel fixed point radial basis function (RBF) artificial neural network (ANN), implemented in a field programmable gate array (FPGA) trained online with a least mean square (LMS) algorithm. The processing time and occupied area were analyzed for various fixed point formats....

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Detalles Bibliográficos
Autores principales: de Souza, Alisson C. D., Fernandes, Marcelo A. C.
Formato: Online Artículo Texto
Lenguaje:English
Publicado: MDPI 2014
Materias:
Article
Acceso en línea:https://www.ncbi.nlm.nih.gov/pmc/articles/PMC4239954/
https://www.ncbi.nlm.nih.gov/pubmed/25268918
http://dx.doi.org/10.3390/s141018223
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author de Souza, Alisson C. D.
Fernandes, Marcelo A. C.
author_facet de Souza, Alisson C. D.
Fernandes, Marcelo A. C.
author_sort de Souza, Alisson C. D.
collection PubMed
description This paper proposes a parallel fixed point radial basis function (RBF) artificial neural network (ANN), implemented in a field programmable gate array (FPGA) trained online with a least mean square (LMS) algorithm. The processing time and occupied area were analyzed for various fixed point formats. The problems of precision of the ANN response for nonlinear classification using the XOR gate and interpolation using the sine function were also analyzed in a hardware implementation. The entire project was developed using the System Generator platform (Xilinx), with a Virtex-6 xc6vcx240t-1ff1156 as the target FPGA.
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spelling pubmed-42399542014-11-21 Parallel Fixed Point Implementation of a Radial Basis Function Network in an FPGA de Souza, Alisson C. D. Fernandes, Marcelo A. C. Sensors (Basel) Article This paper proposes a parallel fixed point radial basis function (RBF) artificial neural network (ANN), implemented in a field programmable gate array (FPGA) trained online with a least mean square (LMS) algorithm. The processing time and occupied area were analyzed for various fixed point formats. The problems of precision of the ANN response for nonlinear classification using the XOR gate and interpolation using the sine function were also analyzed in a hardware implementation. The entire project was developed using the System Generator platform (Xilinx), with a Virtex-6 xc6vcx240t-1ff1156 as the target FPGA. MDPI 2014-09-29 /pmc/articles/PMC4239954/ /pubmed/25268918 http://dx.doi.org/10.3390/s141018223 Text en © 2014 by the authors; licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution license (http://creativecommons.org/licenses/by/4.0/).
spellingShingle Article
de Souza, Alisson C. D.
Fernandes, Marcelo A. C.
Parallel Fixed Point Implementation of a Radial Basis Function Network in an FPGA
title Parallel Fixed Point Implementation of a Radial Basis Function Network in an FPGA
title_full Parallel Fixed Point Implementation of a Radial Basis Function Network in an FPGA
title_fullStr Parallel Fixed Point Implementation of a Radial Basis Function Network in an FPGA
title_full_unstemmed Parallel Fixed Point Implementation of a Radial Basis Function Network in an FPGA
title_short Parallel Fixed Point Implementation of a Radial Basis Function Network in an FPGA
title_sort parallel fixed point implementation of a radial basis function network in an fpga
topic Article
url https://www.ncbi.nlm.nih.gov/pmc/articles/PMC4239954/
https://www.ncbi.nlm.nih.gov/pubmed/25268918
http://dx.doi.org/10.3390/s141018223
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