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Accurate dynamic power estimation for CMOS combinational logic circuits with real gate delay model
Dynamic power estimation is essential in designing VLSI circuits where many parameters are involved but the only circuit parameter that is related to the circuit operation is the nodes’ toggle rate. This paper discusses a deterministic and fast method to estimate the dynamic power consumption for CM...
| Autores principales: | , , , , |
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| Formato: | Online Artículo Texto |
| Lenguaje: | English |
| Publicado: |
Elsevier
2016
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| Materias: | |
| Acceso en línea: | https://www.ncbi.nlm.nih.gov/pmc/articles/PMC4703485/ https://www.ncbi.nlm.nih.gov/pubmed/26843974 http://dx.doi.org/10.1016/j.jare.2015.02.006 |