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Area/latency optimized early output asynchronous full adders and relative-timed ripple carry adders
This article presents two area/latency optimized gate level asynchronous full adder designs which correspond to early output logic. The proposed full adders are constructed using the delay-insensitive dual-rail code and adhere to the four-phase return-to-zero handshaking. For an asynchronous ripple...
| Autores principales: | , |
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| Formato: | Online Artículo Texto |
| Lenguaje: | English |
| Publicado: |
Springer International Publishing
2016
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| Acceso en línea: | https://www.ncbi.nlm.nih.gov/pmc/articles/PMC4828369/ https://www.ncbi.nlm.nih.gov/pubmed/27104128 http://dx.doi.org/10.1186/s40064-016-2074-z |