Development of Gated Pinned Avalanche Photodiode Pixels for High-Speed Low-Light Imaging

This work explores the benefits of linear-mode avalanche photodiodes (APDs) in high-speed CMOS imaging as compared to different approaches present in literature. Analysis of APDs biased below their breakdown voltage employed in single-photon counting mode is also discussed, showing a potentially interesting alternative to existing Geiger-mode APDs. An overview of the recently presented gated pinned avalanche photodiode pixel concept is provided, as well as the first experimental results on a 8 × 16 pixel test array. Full feasibility of the proposed pixel concept is not demonstrated; however, informative data is obtained from the sensor operating under −32 V substrate bias and clearly exhibiting wavelength-dependent gain in frontside illumination. The readout of the chip designed in standard 130 nm CMOS technology shows no dependence on the high-voltage bias. Readout noise level of 15 [Formula: see text] rms, full well capacity of 8000 [Formula: see text] , and the conversion gain of 75 µV [Formula: see text] are extracted from the photon-transfer measurements. The gain characteristics of the avalanche junction are characterized on separate test diodes showing a multiplication factor of 1.6 for red light in frontside illumination.