Design of a Sub-Picosecond Jitter with Adjustable-Range CMOS Delay-Locked Loop for High-Speed and Low-Power Applications

A Delay-Locked Loop (DLL) with a modified charge pump circuit is proposed for generating high-resolution linear delay steps with sub-picosecond jitter performance and adjustable delay range. The small-signal model of the modified charge pump circuit is analyzed to bring forth the relationship betwee...

Descripción completa

Detalles Bibliográficos
Autores principales: Abdulrazzaq, Bilal I., Ibrahim, Omar J., Kawahito, Shoji, Sidek, Roslina M., Shafie, Suhaidi, Yunus, Nurul Amziah Md., Lee, Lini, Halin, Izhal Abdul
Formato: Online Artículo Texto
Lenguaje:English
Publicado: MDPI 2016
Materias:
Article
Acceso en línea:https://www.ncbi.nlm.nih.gov/pmc/articles/PMC5087382/
https://www.ncbi.nlm.nih.gov/pubmed/27690040
http://dx.doi.org/10.3390/s16101593

Internet

https://www.ncbi.nlm.nih.gov/pmc/articles/PMC5087382/
https://www.ncbi.nlm.nih.gov/pubmed/27690040
http://dx.doi.org/10.3390/s16101593

Ejemplares similares