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Degradation mechanisms in gate-all-around silicon Nanowire field effect transistor under electrostatic discharge stress – a modeling approach
The failure and degradation mechanisms of gate-all-around silicon nanowire FET subjected to electrostatic discharge (ESD) are investigated through device modeling. Transmission line pulse stress test is simulated and device degradation physics is modeled. The device degradation level, interface stat...
| Autores principales: | , |
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| Formato: | Online Artículo Texto |
| Lenguaje: | English |
| Publicado: |
Korea Nano Technology Research Society
2014
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| Acceso en línea: | https://www.ncbi.nlm.nih.gov/pmc/articles/PMC5270965/ https://www.ncbi.nlm.nih.gov/pubmed/28191394 http://dx.doi.org/10.1186/s40580-014-0011-9 |