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Automated Software Acceleration in Programmable Logic for an Efficient NFFT Algorithm Implementation: A Case Study

Non-equispaced Fast Fourier transform (NFFT) is a very important algorithm in several technological and scientific areas such as synthetic aperture radar, computational photography, medical imaging, telecommunications, seismic analysis and so on. However, its computation complexity is high. In this...

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Detalles Bibliográficos
Autores principales: Rodríguez, Manuel, Magdaleno, Eduardo, Pérez, Fernando, García, Cristhian
Formato: Online Artículo Texto
Lenguaje:English
Publicado: MDPI 2017
Materias:
Acceso en línea:https://www.ncbi.nlm.nih.gov/pmc/articles/PMC5421654/
https://www.ncbi.nlm.nih.gov/pubmed/28350358
http://dx.doi.org/10.3390/s17040694
_version_ 1783234614800678912
author Rodríguez, Manuel
Magdaleno, Eduardo
Pérez, Fernando
García, Cristhian
author_facet Rodríguez, Manuel
Magdaleno, Eduardo
Pérez, Fernando
García, Cristhian
author_sort Rodríguez, Manuel
collection PubMed
description Non-equispaced Fast Fourier transform (NFFT) is a very important algorithm in several technological and scientific areas such as synthetic aperture radar, computational photography, medical imaging, telecommunications, seismic analysis and so on. However, its computation complexity is high. In this paper, we describe an efficient NFFT implementation with a hardware coprocessor using an All-Programmable System-on-Chip (APSoC). This is a hybrid device that employs an Advanced RISC Machine (ARM) as Processing System with Programmable Logic for high-performance digital signal processing through parallelism and pipeline techniques. The algorithm has been coded in C language with pragma directives to optimize the architecture of the system. We have used the very novel Software Develop System-on-Chip (SDSoC) evelopment tool that simplifies the interface and partitioning between hardware and software. This provides shorter development cycles and iterative improvements by exploring several architectures of the global system. The computational results shows that hardware acceleration significantly outperformed the software based implementation.
format Online
Article
Text
id pubmed-5421654
institution National Center for Biotechnology Information
language English
publishDate 2017
publisher MDPI
record_format MEDLINE/PubMed
spelling pubmed-54216542017-05-12 Automated Software Acceleration in Programmable Logic for an Efficient NFFT Algorithm Implementation: A Case Study Rodríguez, Manuel Magdaleno, Eduardo Pérez, Fernando García, Cristhian Sensors (Basel) Article Non-equispaced Fast Fourier transform (NFFT) is a very important algorithm in several technological and scientific areas such as synthetic aperture radar, computational photography, medical imaging, telecommunications, seismic analysis and so on. However, its computation complexity is high. In this paper, we describe an efficient NFFT implementation with a hardware coprocessor using an All-Programmable System-on-Chip (APSoC). This is a hybrid device that employs an Advanced RISC Machine (ARM) as Processing System with Programmable Logic for high-performance digital signal processing through parallelism and pipeline techniques. The algorithm has been coded in C language with pragma directives to optimize the architecture of the system. We have used the very novel Software Develop System-on-Chip (SDSoC) evelopment tool that simplifies the interface and partitioning between hardware and software. This provides shorter development cycles and iterative improvements by exploring several architectures of the global system. The computational results shows that hardware acceleration significantly outperformed the software based implementation. MDPI 2017-03-28 /pmc/articles/PMC5421654/ /pubmed/28350358 http://dx.doi.org/10.3390/s17040694 Text en © 2017 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/).
spellingShingle Article
Rodríguez, Manuel
Magdaleno, Eduardo
Pérez, Fernando
García, Cristhian
Automated Software Acceleration in Programmable Logic for an Efficient NFFT Algorithm Implementation: A Case Study
title Automated Software Acceleration in Programmable Logic for an Efficient NFFT Algorithm Implementation: A Case Study
title_full Automated Software Acceleration in Programmable Logic for an Efficient NFFT Algorithm Implementation: A Case Study
title_fullStr Automated Software Acceleration in Programmable Logic for an Efficient NFFT Algorithm Implementation: A Case Study
title_full_unstemmed Automated Software Acceleration in Programmable Logic for an Efficient NFFT Algorithm Implementation: A Case Study
title_short Automated Software Acceleration in Programmable Logic for an Efficient NFFT Algorithm Implementation: A Case Study
title_sort automated software acceleration in programmable logic for an efficient nfft algorithm implementation: a case study
topic Article
url https://www.ncbi.nlm.nih.gov/pmc/articles/PMC5421654/
https://www.ncbi.nlm.nih.gov/pubmed/28350358
http://dx.doi.org/10.3390/s17040694
work_keys_str_mv AT rodriguezmanuel automatedsoftwareaccelerationinprogrammablelogicforanefficientnfftalgorithmimplementationacasestudy
AT magdalenoeduardo automatedsoftwareaccelerationinprogrammablelogicforanefficientnfftalgorithmimplementationacasestudy
AT perezfernando automatedsoftwareaccelerationinprogrammablelogicforanefficientnfftalgorithmimplementationacasestudy
AT garciacristhian automatedsoftwareaccelerationinprogrammablelogicforanefficientnfftalgorithmimplementationacasestudy