Arsenic-Doped High-Resistivity-Silicon Epitaxial Layers for Integrating Low-Capacitance Diodes

An arsenic doping technique for depositing up to 40-μm-thick high-resistivity layers is presented for fabricating diodes with low RC constants that can be integrated in closely-packed configurations. The doping of the as-grown epi-layers is controlled down to 5 × 10(11) cm(−3), a value that is solely limited by the cleanness of the epitaxial reactor chamber. To ensure such a low doping concentration, first an As-doped Si seed layer is grown with a concentration of 10(16) to 10(17) cm(−3), after which the dopant gas arsine is turned off and a thick lightly-doped epi-layer is deposited. The final doping in the thick epi-layer relies on the segregation and incorporation of As from the seed layer, and it also depends on the final thickness of the layer, and the exact growth cycles. The obtained epi-layers exhibit a low density of stacking faults, an over-the-wafer doping uniformity of 3.6%, and a lifetime of generated carriers of more than 2.5 ms. Furthermore, the implementation of a segmented photodiode electron detector is demonstrated, featuring a 30 pF capacitance and a 90 Ω series resistance for a 7.6 mm(2) anode area.