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The Programming Optimization of Capacitorless 1T DRAM Based on the Dual-Gate TFET
The larger volume of capacitor and higher leakage current of transistor have become the inherent disadvantages for the traditional one transistor (1T)-one capacitor (1C) dynamic random access memory (DRAM). Recently, the tunneling FET (TFET) is applied in DRAM cell due to the low off-state current a...
| Autores principales: | , , , , |
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| Formato: | Online Artículo Texto |
| Lenguaje: | English |
| Publicado: |
Springer US
2017
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| Materias: | |
| Acceso en línea: | https://www.ncbi.nlm.nih.gov/pmc/articles/PMC5585114/ https://www.ncbi.nlm.nih.gov/pubmed/28875269 http://dx.doi.org/10.1186/s11671-017-2294-3 |