A Low-Noise Direct Incremental A/D Converter for FET-Based THz Imaging Detectors

This paper presents the design, implementation and characterization results of a pixel-level readout chain integrated with a FET-based terahertz (THz) detector for imaging applications. The readout chain is fabricated in a standard 150-nm CMOS technology and contains a cascade of a preamplification and noise reduction stage based on a parametric chopper amplifier and a direct analog-to-digital conversion by means of an incremental [Formula: see text] converter, performing a lock-in operation with modulated sources. The FET detector is integrated with an on-chip antenna operating in the frequency range of 325–375 GHz and compliant with all process design rules. The cascade of the FET THz detector and readout chain is evaluated in terms of responsivity and Noise Equivalent Power (NEP) measurements. The measured readout input-referred noise of 1.6 [Formula: see text] V [Formula: see text] allows preserving the FET detector sensitivity by achieving a minimum NEP of 376 pW/ [Formula: see text] in the optimum bias condition, while directly providing a digital output. The integrated readout chain features 65-dB peak-SNR and 80- [Formula: see text] W power consumption from a 1.8-V supply. The area of the antenna-coupled FET detector and the readout chain fits a pixel pitch of 455 [Formula: see text] m, which is suitable for pixel array implementation. The proposed THz pixel has been successfully applied for imaging of concealed objects in a paper envelope under continuous-wave illumination.