Impact of CMOS Pixel and Electronic Circuitry in the Performance of a Hartmann-Shack Wavefront Sensor

This work presents a numerical simulation of a Hartmann-Shack wavefront sensor (WFS) that assesses the impact of integrated electronic circuitry on the sensor performance, by evaluating a full detection chain encompassing wavefront sampling, photodetection, electronic circuitry and wavefront reconstruction. This platform links dedicated C algorithms for WFS to a SPICE circuit simulator for integrated electronics. The complete codes can be easily replaced in order to represent different detection or reconstruction methods, while the circuit simulator employs reliable models of either off-the-shelf circuit components or custom integrated circuit modules. The most relevant role of this platform is to enable the evaluation of the applicability and constraints of the focal plane of a given wavefront sensor prior to the actual fabrication of the detector chip. In this paper, we will present the simulation results for a Hartmann-Shack wavefront sensor with an orthogonal array of quad-cells (QC) integrated along with active-pixel (active-pixel sensor (APS)) circuitry and analog-to-digital converters (ADC) on a “complementary metal oxide semiconductor” (CMOS) process and deploying a modal wavefront reconstructor. This extended simulation capability for wavefront sensors enables the test and verification of different photosensitive and circuitry topologies for position-sensitive detectors combined with the simulation of sampling microlenses and reconstruction algorithms, with the goal of enhancing the accuracy in the prediction of the wavefront-sensor performance before a detector CMOS chip is actually fabricated.