Towards manufacturing high uniformity polysilicon circuits through TFT contact barrier engineering

The predicted 50 billion devices connected to the Internet of Things by 2020 has renewed interest in polysilicon technology for high performance new sensing and control circuits, in addition to traditional display usage. Yet, the polycrystalline nature of the material presents significant challenges when used in transistors with strongly scaled channel lengths due to non-uniformity in device performance. For these new applications to materialize as viable products, uniform electrical characteristics on large areas will be essential. Here, we report on the effect of deliberately engineered potential barrier at the source of polysilicon thin-film transistors, yielding highly-uniform on-current (<8% device-to-device, accounting for material, as well as substantial geometrical, variations). The contact-controlled architecture of these transistors significantly reduces kink effect and produces high intrinsic gain over a wide range of drain voltage (2–20 V). TCAD simulations associate critical grain boundary position and the two current injection mechanisms in this type of device, showing that, for the geometry considered, the most unfavorable location is ~150 nm inside the source area. At this point, grain boundary contributes to increasing the resistance of the source pinch-off region, reducing the current injection from the bulk of the source area. Nevertheless, the effect is marginal, and the probability of a grain boundary existing at this position is low. This new understanding is instrumental in the design of new signal conversion and gain circuits for flexible and low-power sensors, without the need for complex compensation methods.