Monolithic Low Noise and Low Zero-g Offset CMOS/MEMS Accelerometer Readout Scheme

A monolithic low noise and low zero-g offset CMOS/MEMS accelerometer and readout scheme in standard 0.18 μm CMOS mixed signal UMC process is presented. The low noise chopper architecture and telescopic topology is developed to achieve low noise. The experiments show noise floor is 421.70 μg/√Hz. The...

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Detalles Bibliográficos
Autores principales: Liu, Yu-Sian, Wen, Kuei-Ann
Formato: Online Artículo Texto
Lenguaje:English
Publicado: MDPI 2018
Materias:
Article
Acceso en línea:https://www.ncbi.nlm.nih.gov/pmc/articles/PMC6315608/
https://www.ncbi.nlm.nih.gov/pubmed/30513614
http://dx.doi.org/10.3390/mi9120637
Descripción
Sumario:A monolithic low noise and low zero-g offset CMOS/MEMS accelerometer and readout scheme in standard 0.18 μm CMOS mixed signal UMC process is presented. The low noise chopper architecture and telescopic topology is developed to achieve low noise. The experiments show noise floor is 421.70 μg/√Hz. The whole system has 470 mV/g sensitivity. The power consumption is about 1.67 mW. The zero-g trimming circuit reduces the offset from 1242.63 mg to 2.30 mg.

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