Monolithic Low Noise and Low Zero-g Offset CMOS/MEMS Accelerometer Readout Scheme

A monolithic low noise and low zero-g offset CMOS/MEMS accelerometer and readout scheme in standard 0.18 μm CMOS mixed signal UMC process is presented. The low noise chopper architecture and telescopic topology is developed to achieve low noise. The experiments show noise floor is 421.70 μg/√Hz. The...

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Detalles Bibliográficos
Autores principales: Liu, Yu-Sian, Wen, Kuei-Ann
Formato: Online Artículo Texto
Lenguaje:English
Publicado: MDPI 2018
Materias:
Article
Acceso en línea:https://www.ncbi.nlm.nih.gov/pmc/articles/PMC6315608/
https://www.ncbi.nlm.nih.gov/pubmed/30513614
http://dx.doi.org/10.3390/mi9120637
_version_ 1783384335101984768
author Liu, Yu-Sian
Wen, Kuei-Ann
author_facet Liu, Yu-Sian
Wen, Kuei-Ann
author_sort Liu, Yu-Sian
collection PubMed
description A monolithic low noise and low zero-g offset CMOS/MEMS accelerometer and readout scheme in standard 0.18 μm CMOS mixed signal UMC process is presented. The low noise chopper architecture and telescopic topology is developed to achieve low noise. The experiments show noise floor is 421.70 μg/√Hz. The whole system has 470 mV/g sensitivity. The power consumption is about 1.67 mW. The zero-g trimming circuit reduces the offset from 1242.63 mg to 2.30 mg.
format Online
Article
Text
id pubmed-6315608
institution National Center for Biotechnology Information
language English
publishDate 2018
publisher MDPI
record_format MEDLINE/PubMed
spelling pubmed-63156082019-01-10 Monolithic Low Noise and Low Zero-g Offset CMOS/MEMS Accelerometer Readout Scheme Liu, Yu-Sian Wen, Kuei-Ann Micromachines (Basel) Article A monolithic low noise and low zero-g offset CMOS/MEMS accelerometer and readout scheme in standard 0.18 μm CMOS mixed signal UMC process is presented. The low noise chopper architecture and telescopic topology is developed to achieve low noise. The experiments show noise floor is 421.70 μg/√Hz. The whole system has 470 mV/g sensitivity. The power consumption is about 1.67 mW. The zero-g trimming circuit reduces the offset from 1242.63 mg to 2.30 mg. MDPI 2018-11-30 /pmc/articles/PMC6315608/ /pubmed/30513614 http://dx.doi.org/10.3390/mi9120637 Text en © 2018 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/).
spellingShingle Article
Liu, Yu-Sian
Wen, Kuei-Ann
Monolithic Low Noise and Low Zero-g Offset CMOS/MEMS Accelerometer Readout Scheme
title Monolithic Low Noise and Low Zero-g Offset CMOS/MEMS Accelerometer Readout Scheme
title_full Monolithic Low Noise and Low Zero-g Offset CMOS/MEMS Accelerometer Readout Scheme
title_fullStr Monolithic Low Noise and Low Zero-g Offset CMOS/MEMS Accelerometer Readout Scheme
title_full_unstemmed Monolithic Low Noise and Low Zero-g Offset CMOS/MEMS Accelerometer Readout Scheme
title_short Monolithic Low Noise and Low Zero-g Offset CMOS/MEMS Accelerometer Readout Scheme
title_sort monolithic low noise and low zero-g offset cmos/mems accelerometer readout scheme
topic Article
url https://www.ncbi.nlm.nih.gov/pmc/articles/PMC6315608/
https://www.ncbi.nlm.nih.gov/pubmed/30513614
http://dx.doi.org/10.3390/mi9120637
work_keys_str_mv AT liuyusian monolithiclownoiseandlowzerogoffsetcmosmemsaccelerometerreadoutscheme
AT wenkueiann monolithiclownoiseandlowzerogoffsetcmosmemsaccelerometerreadoutscheme

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