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In-DRAM Cache Management for Low Latency and Low Power 3D-Stacked DRAMs
Recently, 3D-stacked dynamic random access memory (DRAM) has become a promising solution for ultra-high capacity and high-bandwidth memory implementations. However, it also suffers from memory wall problems due to long latency, such as with typical 2D-DRAMs. Although there are various cache manageme...
| Autores principales: | , |
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| Formato: | Online Artículo Texto |
| Lenguaje: | English |
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MDPI
2019
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| Acceso en línea: | https://www.ncbi.nlm.nih.gov/pmc/articles/PMC6412702/ https://www.ncbi.nlm.nih.gov/pubmed/30769837 http://dx.doi.org/10.3390/mi10020124 |