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Fine-Grained Power Gating Using an MRAM-CMOS Non-Volatile Flip-Flop

An area-efficient non-volatile flip flop (NVFF) is proposed. Two minimum-sized Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) and two magnetic tunnel junction (MTJ) devices are added on top of a conventional D flip-flop for temporary storage during the power-down. An area overhead of the...

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Detalles Bibliográficos
Autores principales:	Park, Jaeyoung, Yim, Young Uk
Formato:	Online Artículo Texto
Lenguaje:	English
Publicado:	MDPI 2019
Materias:	Article
Acceso en línea:	https://www.ncbi.nlm.nih.gov/pmc/articles/PMC6630612/ https://www.ncbi.nlm.nih.gov/pubmed/31226793 http://dx.doi.org/10.3390/mi10060411

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