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Variance Reduction during the Fabrication of Sub-20 nm Si Cylindrical Nanopillars for Vertical Gate-All-Around Metal-Oxide-Semiconductor Field-Effect Transistors
[Image: see text] The variance of sub-20 nm devices is a critical issue for large-scale integrated circuits. In this work, uniform sub-20 nm Si nanopillar (NP) arrays with a reduced diameter variance (to ±0.5 nm) and a cylindrical shape, which can be used for vertical gate-all-around metal-oxide-sem...
| Autores principales: | , , |
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| Formato: | Online Artículo Texto |
| Lenguaje: | English |
| Publicado: |
American Chemical Society
2019
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| Acceso en línea: | https://www.ncbi.nlm.nih.gov/pmc/articles/PMC6921678/ https://www.ncbi.nlm.nih.gov/pubmed/31867504 http://dx.doi.org/10.1021/acsomega.9b02520 |