Probing Charge Transport Difference in Parallel and Vertical Layered Electronics with Thin Graphite Source/Drain Contacts

In the present study, we aim to help improve the design of van der Waals stacking, i.e., vertical 2D electronics, by probing charge transport differences in both parallel and vertical conducting channels of layered molybdenum disulfide (MoS(2)), with thin graphite acting as source and drain electrodes. To avoid systematic errors and variable contact contributions to the MoS(2) channel, parallel and vertical electronics are all fabricated and measured on the same conducting material. Large differences in the on/off current ratio, mobility, and charge fluctuations, between parallel and vertical electronics are evident in electrical performance as well as in charge transport mechanisms. Further insights are drawn from a well-constrained analysis of both temperature-dependent current-voltage characteristics and low-frequency (LF) current fluctuations. This work offers significant insight into the fundamental understanding of charge transport and the development of future layered-materials-based integration technology.