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NaviSoC: High-Accuracy Low-Power GNSS SoC with an Integrated Application Processor
A dual-frequency all-in-one Global Navigation Satellite System (GNSS) receiver with a multi-core 32-bit RISC (reduced instruction set computing) application processor was integrated and manufactured as a System-on-Chip (SoC) in a 110 nm CMOS (complementary metal-oxide semiconductor) process. The GNS...
Autores principales: | , , , , , , , , , , , |
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Formato: | Online Artículo Texto |
Lenguaje: | English |
Publicado: |
MDPI
2020
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Materias: | |
Acceso en línea: | https://www.ncbi.nlm.nih.gov/pmc/articles/PMC7070975/ https://www.ncbi.nlm.nih.gov/pubmed/32079088 http://dx.doi.org/10.3390/s20041069 |
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author | Borejko, Tomasz Marcinek, Krzysztof Siwiec, Krzysztof Narczyk, Paweł Borkowski, Adam Butryn, Igor Łuczyk, Arkadiusz Pietroń, Daniel Plasota, Maciej Reszewicz, Szymon Wiechowski, Łukasz Pleskacz, Witold A. |
author_facet | Borejko, Tomasz Marcinek, Krzysztof Siwiec, Krzysztof Narczyk, Paweł Borkowski, Adam Butryn, Igor Łuczyk, Arkadiusz Pietroń, Daniel Plasota, Maciej Reszewicz, Szymon Wiechowski, Łukasz Pleskacz, Witold A. |
author_sort | Borejko, Tomasz |
collection | PubMed |
description | A dual-frequency all-in-one Global Navigation Satellite System (GNSS) receiver with a multi-core 32-bit RISC (reduced instruction set computing) application processor was integrated and manufactured as a System-on-Chip (SoC) in a 110 nm CMOS (complementary metal-oxide semiconductor) process. The GNSS RF (radio frequency) front-end with baseband navigation engine is able to receive, simultaneously, Galileo (European Global Satellite Navigation System) E1/E5ab, GPS (US Global Positioning System) L1/L1C/L5, BeiDou (Chinese Navigation Satellite System) B1/B2, GLONASS (GLObal NAvigation Satellite System of Russian Government) L1/L3/L5, QZSS (Quasi-Zenith Satellite System development by the Japanese government) L1/L5 and IRNSS (Indian Regional Navigation Satellite System) L5, as well as all SBAS (Satellite Based Augmentation System) signals. The ability of the GNSS to detect such a broad range of signals allows for high-accuracy positioning. The whole SoC (system-on-chip), which is connected to a small passive antenna, provides precise position, velocity and time or raw GNSS data for hybridization with the IMU (inertial measurement unit) without the need for an external application processor. Additionally, user application can be executed directly in the SoC. It works in the −40 to +105 °C temperature range with a 1.5 V supply. The assembled test-chip takes 100 pins in a QFN (quad-flat no-leads) package and needs only a quartz crystal for the on-chip reference clock driver and optional SAW (surface acoustic wave) filters. The radio performance for both wideband (52 MHz) channels centered at L1/E1 and L5/E5 is NF = 2.3 dB, G = 131 dB, with 121 dBc/Hz of phase noise @ 1 MHz offset from the carrier, consumes 35 mW and occupies a 4.5 mm(2) silicon area. The SoC reported in the paper is the first ever dual-frequency single-chip GNSS receiver equipped with a multi-core application microcontroller integrated with embedded flash memory for the user application program. |
format | Online Article Text |
id | pubmed-7070975 |
institution | National Center for Biotechnology Information |
language | English |
publishDate | 2020 |
publisher | MDPI |
record_format | MEDLINE/PubMed |
spelling | pubmed-70709752020-03-19 NaviSoC: High-Accuracy Low-Power GNSS SoC with an Integrated Application Processor Borejko, Tomasz Marcinek, Krzysztof Siwiec, Krzysztof Narczyk, Paweł Borkowski, Adam Butryn, Igor Łuczyk, Arkadiusz Pietroń, Daniel Plasota, Maciej Reszewicz, Szymon Wiechowski, Łukasz Pleskacz, Witold A. Sensors (Basel) Article A dual-frequency all-in-one Global Navigation Satellite System (GNSS) receiver with a multi-core 32-bit RISC (reduced instruction set computing) application processor was integrated and manufactured as a System-on-Chip (SoC) in a 110 nm CMOS (complementary metal-oxide semiconductor) process. The GNSS RF (radio frequency) front-end with baseband navigation engine is able to receive, simultaneously, Galileo (European Global Satellite Navigation System) E1/E5ab, GPS (US Global Positioning System) L1/L1C/L5, BeiDou (Chinese Navigation Satellite System) B1/B2, GLONASS (GLObal NAvigation Satellite System of Russian Government) L1/L3/L5, QZSS (Quasi-Zenith Satellite System development by the Japanese government) L1/L5 and IRNSS (Indian Regional Navigation Satellite System) L5, as well as all SBAS (Satellite Based Augmentation System) signals. The ability of the GNSS to detect such a broad range of signals allows for high-accuracy positioning. The whole SoC (system-on-chip), which is connected to a small passive antenna, provides precise position, velocity and time or raw GNSS data for hybridization with the IMU (inertial measurement unit) without the need for an external application processor. Additionally, user application can be executed directly in the SoC. It works in the −40 to +105 °C temperature range with a 1.5 V supply. The assembled test-chip takes 100 pins in a QFN (quad-flat no-leads) package and needs only a quartz crystal for the on-chip reference clock driver and optional SAW (surface acoustic wave) filters. The radio performance for both wideband (52 MHz) channels centered at L1/E1 and L5/E5 is NF = 2.3 dB, G = 131 dB, with 121 dBc/Hz of phase noise @ 1 MHz offset from the carrier, consumes 35 mW and occupies a 4.5 mm(2) silicon area. The SoC reported in the paper is the first ever dual-frequency single-chip GNSS receiver equipped with a multi-core application microcontroller integrated with embedded flash memory for the user application program. MDPI 2020-02-16 /pmc/articles/PMC7070975/ /pubmed/32079088 http://dx.doi.org/10.3390/s20041069 Text en © 2020 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/). |
spellingShingle | Article Borejko, Tomasz Marcinek, Krzysztof Siwiec, Krzysztof Narczyk, Paweł Borkowski, Adam Butryn, Igor Łuczyk, Arkadiusz Pietroń, Daniel Plasota, Maciej Reszewicz, Szymon Wiechowski, Łukasz Pleskacz, Witold A. NaviSoC: High-Accuracy Low-Power GNSS SoC with an Integrated Application Processor |
title | NaviSoC: High-Accuracy Low-Power GNSS SoC with an Integrated Application Processor |
title_full | NaviSoC: High-Accuracy Low-Power GNSS SoC with an Integrated Application Processor |
title_fullStr | NaviSoC: High-Accuracy Low-Power GNSS SoC with an Integrated Application Processor |
title_full_unstemmed | NaviSoC: High-Accuracy Low-Power GNSS SoC with an Integrated Application Processor |
title_short | NaviSoC: High-Accuracy Low-Power GNSS SoC with an Integrated Application Processor |
title_sort | navisoc: high-accuracy low-power gnss soc with an integrated application processor |
topic | Article |
url | https://www.ncbi.nlm.nih.gov/pmc/articles/PMC7070975/ https://www.ncbi.nlm.nih.gov/pubmed/32079088 http://dx.doi.org/10.3390/s20041069 |
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