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Accelerated Tests on Si and SiC Power Transistors with Thermal, Fastand Ultra-Fast Neutrons

Neutron test campaigns on silicon (Si) and silicon carbide (SiC) power MOSFETs and IGBTs were conducted at the TRIGA (Training, Research, Isotopes, General Atomics) Mark II (Pavia, Italy) nuclear reactor and ChipIr-ISIS Neutron and Muon Source (Didcot, U.K.) facility. About 2000 power transistors ma...

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Autores principales: Principato, Fabio, Altieri, Saverio, Abbene, Leonardo, Pintacuda, Francesco
Formato: Online Artículo Texto
Lenguaje:English
Publicado: MDPI 2020
Materias:
Acceso en línea:https://www.ncbi.nlm.nih.gov/pmc/articles/PMC7309113/
https://www.ncbi.nlm.nih.gov/pubmed/32466560
http://dx.doi.org/10.3390/s20113021
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author Principato, Fabio
Altieri, Saverio
Abbene, Leonardo
Pintacuda, Francesco
author_facet Principato, Fabio
Altieri, Saverio
Abbene, Leonardo
Pintacuda, Francesco
author_sort Principato, Fabio
collection PubMed
description Neutron test campaigns on silicon (Si) and silicon carbide (SiC) power MOSFETs and IGBTs were conducted at the TRIGA (Training, Research, Isotopes, General Atomics) Mark II (Pavia, Italy) nuclear reactor and ChipIr-ISIS Neutron and Muon Source (Didcot, U.K.) facility. About 2000 power transistors made by STMicroelectronics were tested in all the experiments. Tests with thermal and fast neutrons (up to about 10 MeV) at the TRIGA Mark II reactor showed that single-event burnout (SEB) failures only occurred at voltages close to the rated drain-source voltage. Thermal neutrons did not induce SEB, nor degradation in the electrical parameters of the devices. SEB failures during testing at ChipIr with ultra-fast neutrons (1-800 MeV) were evaluated in terms of failure in time (FIT) versus derating voltage curves according to the JEP151 procedure of the Joint Electron Device Engineering Council (JEDEC). These curves, even if scaled with die size and avalanche voltage, were strongly linked to the technological processes of the devices, although a common trend was observed that highlighted commonalities among the failures of different types of MOSFETs. In both experiments, we observed only SEB failures without single-event gate rupture (SEGR) during the tests. None of the power devices that survived the neutron tests were degraded in their electrical performances. A study of the worst-case bias condition (gate and/or drain) during irradiation was performed.
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spelling pubmed-73091132020-06-25 Accelerated Tests on Si and SiC Power Transistors with Thermal, Fastand Ultra-Fast Neutrons Principato, Fabio Altieri, Saverio Abbene, Leonardo Pintacuda, Francesco Sensors (Basel) Article Neutron test campaigns on silicon (Si) and silicon carbide (SiC) power MOSFETs and IGBTs were conducted at the TRIGA (Training, Research, Isotopes, General Atomics) Mark II (Pavia, Italy) nuclear reactor and ChipIr-ISIS Neutron and Muon Source (Didcot, U.K.) facility. About 2000 power transistors made by STMicroelectronics were tested in all the experiments. Tests with thermal and fast neutrons (up to about 10 MeV) at the TRIGA Mark II reactor showed that single-event burnout (SEB) failures only occurred at voltages close to the rated drain-source voltage. Thermal neutrons did not induce SEB, nor degradation in the electrical parameters of the devices. SEB failures during testing at ChipIr with ultra-fast neutrons (1-800 MeV) were evaluated in terms of failure in time (FIT) versus derating voltage curves according to the JEP151 procedure of the Joint Electron Device Engineering Council (JEDEC). These curves, even if scaled with die size and avalanche voltage, were strongly linked to the technological processes of the devices, although a common trend was observed that highlighted commonalities among the failures of different types of MOSFETs. In both experiments, we observed only SEB failures without single-event gate rupture (SEGR) during the tests. None of the power devices that survived the neutron tests were degraded in their electrical performances. A study of the worst-case bias condition (gate and/or drain) during irradiation was performed. MDPI 2020-05-26 /pmc/articles/PMC7309113/ /pubmed/32466560 http://dx.doi.org/10.3390/s20113021 Text en © 2020 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/).
spellingShingle Article
Principato, Fabio
Altieri, Saverio
Abbene, Leonardo
Pintacuda, Francesco
Accelerated Tests on Si and SiC Power Transistors with Thermal, Fastand Ultra-Fast Neutrons
title Accelerated Tests on Si and SiC Power Transistors with Thermal, Fastand Ultra-Fast Neutrons
title_full Accelerated Tests on Si and SiC Power Transistors with Thermal, Fastand Ultra-Fast Neutrons
title_fullStr Accelerated Tests on Si and SiC Power Transistors with Thermal, Fastand Ultra-Fast Neutrons
title_full_unstemmed Accelerated Tests on Si and SiC Power Transistors with Thermal, Fastand Ultra-Fast Neutrons
title_short Accelerated Tests on Si and SiC Power Transistors with Thermal, Fastand Ultra-Fast Neutrons
title_sort accelerated tests on si and sic power transistors with thermal, fastand ultra-fast neutrons
topic Article
url https://www.ncbi.nlm.nih.gov/pmc/articles/PMC7309113/
https://www.ncbi.nlm.nih.gov/pubmed/32466560
http://dx.doi.org/10.3390/s20113021
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