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Event-Based Gesture Recognition through a Hierarchy of Time-Surfaces for FPGA
Neuromorphic vision sensors detect changes in luminosity taking inspiration from mammalian retina and providing a stream of events with high temporal resolution, also known as Dynamic Vision Sensors (DVS). This continuous stream of events can be used to extract spatio-temporal patterns from a scene....
Autores principales: | , , , , , |
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Formato: | Online Artículo Texto |
Lenguaje: | English |
Publicado: |
MDPI
2020
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Materias: | |
Acceso en línea: | https://www.ncbi.nlm.nih.gov/pmc/articles/PMC7349403/ https://www.ncbi.nlm.nih.gov/pubmed/32560238 http://dx.doi.org/10.3390/s20123404 |
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author | Tapiador-Morales, Ricardo Maro, Jean-Matthieu Jimenez-Fernandez, Angel Jimenez-Moreno, Gabriel Benosman, Ryad Linares-Barranco, Alejandro |
author_facet | Tapiador-Morales, Ricardo Maro, Jean-Matthieu Jimenez-Fernandez, Angel Jimenez-Moreno, Gabriel Benosman, Ryad Linares-Barranco, Alejandro |
author_sort | Tapiador-Morales, Ricardo |
collection | PubMed |
description | Neuromorphic vision sensors detect changes in luminosity taking inspiration from mammalian retina and providing a stream of events with high temporal resolution, also known as Dynamic Vision Sensors (DVS). This continuous stream of events can be used to extract spatio-temporal patterns from a scene. A time-surface represents a spatio-temporal context for a given spatial radius around an incoming event from a sensor at a specific time history. Time-surfaces can be organized in a hierarchical way to extract features from input events using the Hierarchy Of Time-Surfaces algorithm, hereinafter HOTS. HOTS can be organized in consecutive layers to extract combination of features in a similar way as some deep-learning algorithms do. This work introduces a novel FPGA architecture for accelerating HOTS network. This architecture is mainly based on block-RAM memory and the non-restoring square root algorithm, requiring basic components and enabling it for low-power low-latency embedded applications. The presented architecture has been tested on a Zynq 7100 platform at 100 MHz. The results show that the latencies are in the range of 1 [Formula: see text] s to 6.7 [Formula: see text] s, requiring a maximum dynamic power consumption of 77 mW. This system was tested with a gesture recognition dataset, obtaining an accuracy loss for 16-bit precision of only 1.2% with respect to the original software HOTS. |
format | Online Article Text |
id | pubmed-7349403 |
institution | National Center for Biotechnology Information |
language | English |
publishDate | 2020 |
publisher | MDPI |
record_format | MEDLINE/PubMed |
spelling | pubmed-73494032020-07-22 Event-Based Gesture Recognition through a Hierarchy of Time-Surfaces for FPGA Tapiador-Morales, Ricardo Maro, Jean-Matthieu Jimenez-Fernandez, Angel Jimenez-Moreno, Gabriel Benosman, Ryad Linares-Barranco, Alejandro Sensors (Basel) Article Neuromorphic vision sensors detect changes in luminosity taking inspiration from mammalian retina and providing a stream of events with high temporal resolution, also known as Dynamic Vision Sensors (DVS). This continuous stream of events can be used to extract spatio-temporal patterns from a scene. A time-surface represents a spatio-temporal context for a given spatial radius around an incoming event from a sensor at a specific time history. Time-surfaces can be organized in a hierarchical way to extract features from input events using the Hierarchy Of Time-Surfaces algorithm, hereinafter HOTS. HOTS can be organized in consecutive layers to extract combination of features in a similar way as some deep-learning algorithms do. This work introduces a novel FPGA architecture for accelerating HOTS network. This architecture is mainly based on block-RAM memory and the non-restoring square root algorithm, requiring basic components and enabling it for low-power low-latency embedded applications. The presented architecture has been tested on a Zynq 7100 platform at 100 MHz. The results show that the latencies are in the range of 1 [Formula: see text] s to 6.7 [Formula: see text] s, requiring a maximum dynamic power consumption of 77 mW. This system was tested with a gesture recognition dataset, obtaining an accuracy loss for 16-bit precision of only 1.2% with respect to the original software HOTS. MDPI 2020-06-16 /pmc/articles/PMC7349403/ /pubmed/32560238 http://dx.doi.org/10.3390/s20123404 Text en © 2020 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/). |
spellingShingle | Article Tapiador-Morales, Ricardo Maro, Jean-Matthieu Jimenez-Fernandez, Angel Jimenez-Moreno, Gabriel Benosman, Ryad Linares-Barranco, Alejandro Event-Based Gesture Recognition through a Hierarchy of Time-Surfaces for FPGA |
title | Event-Based Gesture Recognition through a Hierarchy of Time-Surfaces for FPGA |
title_full | Event-Based Gesture Recognition through a Hierarchy of Time-Surfaces for FPGA |
title_fullStr | Event-Based Gesture Recognition through a Hierarchy of Time-Surfaces for FPGA |
title_full_unstemmed | Event-Based Gesture Recognition through a Hierarchy of Time-Surfaces for FPGA |
title_short | Event-Based Gesture Recognition through a Hierarchy of Time-Surfaces for FPGA |
title_sort | event-based gesture recognition through a hierarchy of time-surfaces for fpga |
topic | Article |
url | https://www.ncbi.nlm.nih.gov/pmc/articles/PMC7349403/ https://www.ncbi.nlm.nih.gov/pubmed/32560238 http://dx.doi.org/10.3390/s20123404 |
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