High-Efficiency Silicon Inverted Pyramid-Based Passivated Emitter and Rear Cells

Surface texturing is one of the most important techniques for improving the performance of photovoltaic (PV) device. As an appealing front texture, inverted pyramid (IP) has attracted lots of research interests due to its superior antireflection effect and structural characteristics. In this paper, we prepare high-uniform silicon (Si) IPs structures on a commercial monocrystalline silicon wafer with a standard size of 156 × 156 mm(2) employing the metal-assisted chemical etching (MACE) and alkali anisotropic etching technique. Combining the front IPs textures with the rear surface passivation of Al(2)O(3)/SiN(x), we fabricate a novel Si IP-based passivated emitter and rear cell (PERC). Benefiting from the optical superiority of the optimized IPs and the improvement of electrical performance of the device, we achieve a high efficiency of 21.4% of the Si IP-based PERC, which is comparable with the average efficiency of the commercial PERC solar cells. The optimizing morphology of IP textures is the key to the improvement of the short circuit current I(sc) from 9.51 A to 9.63 A; meanwhile, simultaneous stack SiO(2)/SiN(x) passivation for the Si IP-based n(+) emitter and stack Al(2)O(3)/SiN(x) passivation for rear surface guarantees a high open-circuit voltage V(oc) of 0.677 V. The achievement of this high-performance PV device demonstrates a competitive texturing technique and a promising prospect for the mass production of the Si IP-based PERC.