Investigation of Monolithic 3D Integrated Circuit Inverter with Feedback Field Effect Transistors Using TCAD Simulation

The optimal structure and process for the feedback field-effect transistor (FBFET) to operate as a logic device are investigated by using a technology computer-aided design mixed-mode simulator. To minimize the memory window of the FBFET, the channel length (L(ch)), thickness of silicon body (T(si)), and doping concentration (N(ch)) of the channel region below the gate are adjusted. As a result, the memory window increases as L(ch) and T(si) increase, and the memory window is minimum when N(ch) is approximately 9 × 10(19) cm(−3). The electrical coupling between the top and bottom tiers of a monolithic 3-dimensional inverter (M3DINV) consisting of an n-type FBFET located at the top tier and a p-type FBFET located at the bottom tier is also investigated. In the M3DINV, we investigate variation of switching voltage with respect to voltage transfer characteristics (VTC), with different thickness values of interlayer dielectrics (T(ILD)), T(si), L(ch), and N(ch). The variation of propagation delay of the M3DINV with different T(ILD), T(si), L(ch), and N(ch) is also investigated. As a result, the electrical coupling between the stacked FBFETs by T(ILD) can be neglected. The switching voltage gaps increase as L(ch) and T(si) increase and decrease, respectively. Furthermore, the slopes of VTC of M3DINV increase as T(si) and N(ch) increase. For transient response, t(pHL) decrease as L(ch), T(si), and N(ch) increase, but t(pLH) increase as L(ch) and T(si) increase and it is almost the same for N(ch).