Circuit Simulation Considering Electrical Coupling in Monolithic 3D Logics with Junctionless FETs

The junctionless field-effect transistor (JLFET) compact model using the model parameters extracted from the LETI-UTSOI (version 2.1) model was proposed to perform circuit simulation considering the electrical coupling between the stacked JLFETs of a monolithic 3D integrated circuit (M3DIC) composed...

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Detalles Bibliográficos
Autores principales: Ahn, Tae Jun, Yu, Yun Seop
Formato: Online Artículo Texto
Lenguaje:English
Publicado: MDPI 2020
Materias:
Article
Acceso en línea:https://www.ncbi.nlm.nih.gov/pmc/articles/PMC7598614/
https://www.ncbi.nlm.nih.gov/pubmed/32987731
http://dx.doi.org/10.3390/mi11100887

Internet

https://www.ncbi.nlm.nih.gov/pmc/articles/PMC7598614/
https://www.ncbi.nlm.nih.gov/pubmed/32987731
http://dx.doi.org/10.3390/mi11100887

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