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A Multi-Core Object Detection Coprocessor for Multi-Scale/Type Classification Applicable to IoT Devices

Power efficiency is becoming a critical aspect of IoT devices. In this paper, we present a compact object-detection coprocessor with multiple cores for multi-scale/type classification. This coprocessor is capable to process scalable block size for multi-shape detection-window and can be compatible w...

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Detalles Bibliográficos
Autores principales: Xu, Peng, Xiao, Zhihua, Wang, Xianglong, Chen, Lei, Wang, Chao, An, Fengwei
Formato: Online Artículo Texto
Lenguaje:English
Publicado: MDPI 2020
Materias:
Acceso en línea:https://www.ncbi.nlm.nih.gov/pmc/articles/PMC7662932/
https://www.ncbi.nlm.nih.gov/pubmed/33142931
http://dx.doi.org/10.3390/s20216239
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author Xu, Peng
Xiao, Zhihua
Wang, Xianglong
Chen, Lei
Wang, Chao
An, Fengwei
author_facet Xu, Peng
Xiao, Zhihua
Wang, Xianglong
Chen, Lei
Wang, Chao
An, Fengwei
author_sort Xu, Peng
collection PubMed
description Power efficiency is becoming a critical aspect of IoT devices. In this paper, we present a compact object-detection coprocessor with multiple cores for multi-scale/type classification. This coprocessor is capable to process scalable block size for multi-shape detection-window and can be compatible with the frame-image sizes up to 2048 × 2048 for multi-scale classification. A memory-reuse strategy that requires only one dual-port SRAM for storing the feature-vector of one-row blocks is developed to save memory usage. Eventually, a prototype platform is implemented on the Intel DE4 development board with the Stratix IV device. The power consumption of each core in FPGA is only 80.98 mW.
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spelling pubmed-76629322020-11-14 A Multi-Core Object Detection Coprocessor for Multi-Scale/Type Classification Applicable to IoT Devices Xu, Peng Xiao, Zhihua Wang, Xianglong Chen, Lei Wang, Chao An, Fengwei Sensors (Basel) Article Power efficiency is becoming a critical aspect of IoT devices. In this paper, we present a compact object-detection coprocessor with multiple cores for multi-scale/type classification. This coprocessor is capable to process scalable block size for multi-shape detection-window and can be compatible with the frame-image sizes up to 2048 × 2048 for multi-scale classification. A memory-reuse strategy that requires only one dual-port SRAM for storing the feature-vector of one-row blocks is developed to save memory usage. Eventually, a prototype platform is implemented on the Intel DE4 development board with the Stratix IV device. The power consumption of each core in FPGA is only 80.98 mW. MDPI 2020-10-31 /pmc/articles/PMC7662932/ /pubmed/33142931 http://dx.doi.org/10.3390/s20216239 Text en © 2020 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/).
spellingShingle Article
Xu, Peng
Xiao, Zhihua
Wang, Xianglong
Chen, Lei
Wang, Chao
An, Fengwei
A Multi-Core Object Detection Coprocessor for Multi-Scale/Type Classification Applicable to IoT Devices
title A Multi-Core Object Detection Coprocessor for Multi-Scale/Type Classification Applicable to IoT Devices
title_full A Multi-Core Object Detection Coprocessor for Multi-Scale/Type Classification Applicable to IoT Devices
title_fullStr A Multi-Core Object Detection Coprocessor for Multi-Scale/Type Classification Applicable to IoT Devices
title_full_unstemmed A Multi-Core Object Detection Coprocessor for Multi-Scale/Type Classification Applicable to IoT Devices
title_short A Multi-Core Object Detection Coprocessor for Multi-Scale/Type Classification Applicable to IoT Devices
title_sort multi-core object detection coprocessor for multi-scale/type classification applicable to iot devices
topic Article
url https://www.ncbi.nlm.nih.gov/pmc/articles/PMC7662932/
https://www.ncbi.nlm.nih.gov/pubmed/33142931
http://dx.doi.org/10.3390/s20216239
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