Digitally Controlled Oscillator with High Timing Resolution and Low Complexity for Clock Generation †

This paper presents a digitally controlled oscillator (DCO) with a low-complexity circuit structure that combines multiple delay circuits to achieve a high timing resolution and wide output frequency range simultaneously while also significantly reducing the overall power consumption. A 0.18 µm complementary metal–oxide–semiconductor standard process was used for the design, and measurements showed that the chip had a minimum controllable timing resolution of 4.81 ps and power consumption of 142 µW with an output signal of 364 MHz. When compared with other designs using advanced processes, the proposed DCO demonstrated the best power-to-frequency ratio. Therefore, it can output a signal at the required frequency more efficiently in terms of power consumption. Additionally, because the proposed DCO uses digital logic gates only, a cell-based design flow can be implemented. Hence, the proposed DCO is not only easy to implement in different processes but also easy to integrate with other digital circuits.