Optimization of Structure and Electrical Characteristics for Four-Layer Vertically-Stacked Horizontal Gate-All-Around Si Nanosheets Devices

In this paper, the optimizations of vertically-stacked horizontal gate-all-around (GAA) Si nanosheet (NS) transistors on bulk Si substrate are systemically investigated. The release process of NS channels was firstly optimized to achieve uniform device structures. An over 100:1 selective wet-etch ra...

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Detalles Bibliográficos
Autores principales: Zhang, Qingzhu, Gu, Jie, Xu, Renren, Cao, Lei, Li, Junjie, Wu, Zhenhua, Wang, Guilei, Yao, Jiaxin, Zhang, Zhaohao, Xiang, Jinjuan, He, Xiaobin, Kong, Zhenzhen, Yang, Hong, Tian, Jiajia, Xu, Gaobo, Mao, Shujuan, Radamson, Henry H., Yin, Huaxiang, Luo, Jun
Formato: Online Artículo Texto
Lenguaje:English
Publicado: MDPI 2021
Materias:
Article
Acceso en línea:https://www.ncbi.nlm.nih.gov/pmc/articles/PMC7998492/
https://www.ncbi.nlm.nih.gov/pubmed/33808024
http://dx.doi.org/10.3390/nano11030646

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