Characterization and Programming Algorithm of Phase Change Memory Cells for Analog In-Memory Computing

In this paper, a thorough characterization of phase-change memory (PCM) cells was carried out, aimed at evaluating and optimizing their performance as enabling devices for analog in-memory computing (AIMC) applications. Exploiting the features of programming pulses, we discuss strategies to reduce undesired phenomena that afflict PCM cells and are particularly harmful in analog computations, such as low-frequency noise, time drift, and cell-to-cell variability of the conductance. The test vehicle is an embedded PCM (ePCM) provided by STMicroelectronics and designed in 90-nm smart power BCD technology with a Ge-rich Ge-Sb-Te (GST) alloy for automotive applications. On the basis of the results of the characterization of a large number of cells, we propose an iterative algorithm to allow multi-level cell conductance programming, and its performances for AIMC applications are discussed. Results for a group of 512 cells programmed with four different conductance levels are presented, showing an initial conductance spread under 6%, relative current noise less than 9% in most cases, and a relative conductance drift of 15% in the worst case after 14 h from the application of the programming sequence.